coredump: add support for ARM Cortex-M
This adds the necessary bits in arch code, and Python scripts to enable coredump support for ARM Cortex-M. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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8 changed files with 180 additions and 0 deletions
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@ -27,6 +27,7 @@ config ARC
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config ARM
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bool
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select ARCH_IS_SET
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select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M
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select HAS_DTS
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# FIXME: current state of the code for all ARM requires this, but
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# is really only necessary for Cortex-M with ARM MPU!
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@ -13,6 +13,8 @@ zephyr_library_sources(
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thread_abort.c
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)
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zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
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if (CONFIG_SW_VECTOR_RELAY)
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if (CONFIG_CPU_CORTEX_M_HAS_VTOR)
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set(relay_vector_table_sort_key relay_vectors)
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75
arch/arm/core/aarch32/cortex_m/coredump.c
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75
arch/arm/core/aarch32/cortex_m/coredump.c
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@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <debug/coredump.h>
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#define ARCH_HDR_VER 1
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uint32_t z_arm_coredump_fault_sp;
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struct arm_arch_block {
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struct {
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r12;
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uint32_t lr;
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uint32_t pc;
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uint32_t xpsr;
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uint32_t sp;
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} r;
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} __packed;
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/*
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* This might be too large for stack space if defined
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* inside function. So do it here.
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*/
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static struct arm_arch_block arch_blk;
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void arch_coredump_info_dump(const z_arch_esf_t *esf)
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{
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struct z_coredump_arch_hdr_t hdr = {
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.id = Z_COREDUMP_ARCH_HDR_ID,
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.hdr_version = ARCH_HDR_VER,
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.num_bytes = sizeof(arch_blk),
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};
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/* Nothing to process */
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if (esf == NULL) {
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return;
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}
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(void)memset(&arch_blk, 0, sizeof(arch_blk));
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/*
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* 17 registers expected by GDB.
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* Not all are in ESF but the GDB stub
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* will need to send all 17 as one packet.
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* The stub will need to send undefined
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* for registers not presented in coredump.
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*/
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arch_blk.r.r0 = esf->basic.r0;
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arch_blk.r.r1 = esf->basic.r1;
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arch_blk.r.r2 = esf->basic.r2;
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arch_blk.r.r3 = esf->basic.r3;
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arch_blk.r.r12 = esf->basic.ip;
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arch_blk.r.lr = esf->basic.lr;
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arch_blk.r.pc = esf->basic.pc;
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arch_blk.r.xpsr = esf->basic.xpsr;
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arch_blk.r.sp = z_arm_coredump_fault_sp;
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/* Send for output */
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z_coredump_buffer_output((uint8_t *)&hdr, sizeof(hdr));
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z_coredump_buffer_output((uint8_t *)&arch_blk, sizeof(arch_blk));
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}
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uint16_t arch_coredump_tgt_code_get(void)
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{
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return COREDUMP_TGT_ARM_CORTEX_M;
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}
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@ -953,6 +953,10 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return)
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__ASSERT(esf != NULL,
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"ESF could not be retrieved successfully. Shall never occur.");
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#ifdef CONFIG_DEBUG_COREDUMP
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z_arm_coredump_fault_sp = POINTER_TO_UINT(esf);
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#endif
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reason = fault_handle(esf, fault, &recoverable);
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if (recoverable) {
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return;
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@ -91,6 +91,8 @@ struct __esf {
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#endif
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};
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extern uint32_t z_arm_coredump_fault_sp;
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typedef struct __esf z_arch_esf_t;
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#ifdef CONFIG_CPU_CORTEX_M
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@ -25,6 +25,7 @@ enum z_coredump_tgt_code {
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COREDUMP_TGT_UNKNOWN = 0,
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COREDUMP_TGT_X86,
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COREDUMP_TGT_X86_64,
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COREDUMP_TGT_ARM_CORTEX_M,
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};
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/* Coredump header */
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@ -6,11 +6,13 @@
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from gdbstubs.arch.x86 import GdbStub_x86
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from gdbstubs.arch.x86_64 import GdbStub_x86_64
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from gdbstubs.arch.arm_cortex_m import GdbStub_ARM_CortexM
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class TgtCode:
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UNKNOWN = 0
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X86 = 1
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X86_64 = 2
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ARM_CORTEX_M = 3
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def get_gdbstub(logfile, elffile):
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stub = None
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@ -21,5 +23,7 @@ def get_gdbstub(logfile, elffile):
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stub = GdbStub_x86(logfile=logfile, elffile=elffile)
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elif tgt_code == TgtCode.X86_64:
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stub = GdbStub_x86_64(logfile=logfile, elffile=elffile)
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elif tgt_code == TgtCode.ARM_CORTEX_M:
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stub = GdbStub_ARM_CortexM(logfile=logfile, elffile=elffile)
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return stub
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91
scripts/coredump/gdbstubs/arch/arm_cortex_m.py
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91
scripts/coredump/gdbstubs/arch/arm_cortex_m.py
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#!/usr/bin/env python3
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#
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# Copyright (c) 2020 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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import binascii
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import logging
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import struct
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from gdbstubs.gdbstub import GdbStub
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logger = logging.getLogger("gdbstub")
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class RegNum():
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R0 = 0
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R1 = 1
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R2 = 2
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R3 = 3
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R4 = 4
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R5 = 5
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R6 = 6
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R7 = 7
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R8 = 8
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R9 = 9
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R10 = 10
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R11 = 11
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R12 = 12
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SP = 13
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LR = 14
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PC = 15
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XPSR = 16
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class GdbStub_ARM_CortexM(GdbStub):
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ARCH_DATA_BLK_STRUCT = "<IIIIIIIII"
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GDB_SIGNAL_DEFAULT = 7
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GDB_G_PKT_NUM_REGS = 17
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def __init__(self, logfile, elffile):
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super().__init__(logfile=logfile, elffile=elffile)
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self.registers = None
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self.gdb_signal = self.GDB_SIGNAL_DEFAULT
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self.parse_arch_data_block()
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def parse_arch_data_block(self):
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arch_data_blk = self.logfile.get_arch_data()['data']
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tu = struct.unpack(self.ARCH_DATA_BLK_STRUCT, arch_data_blk)
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self.registers = dict()
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self.registers[RegNum.R0] = tu[0]
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self.registers[RegNum.R1] = tu[1]
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self.registers[RegNum.R2] = tu[2]
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self.registers[RegNum.R3] = tu[3]
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self.registers[RegNum.R12] = tu[4]
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self.registers[RegNum.LR] = tu[5]
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self.registers[RegNum.PC] = tu[6]
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self.registers[RegNum.XPSR] = tu[7]
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self.registers[RegNum.SP] = tu[8]
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def handle_register_group_read_packet(self):
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reg_fmt = "<I"
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idx = 0
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pkt = b''
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while idx < self.GDB_G_PKT_NUM_REGS:
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if idx in self.registers:
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bval = struct.pack(reg_fmt, self.registers[idx])
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pkt += binascii.hexlify(bval)
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else:
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# Register not in coredump -> unknown value
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# Send in "xxxxxxxx"
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pkt += b'x' * 8
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idx += 1
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self.put_gdb_packet(pkt)
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def handle_register_single_read_packet(self, pkt):
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# Mark registers as "<unavailable>".
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# 'p' packets are usually used for registers
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# other than the general ones (e.g. eax, ebx)
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# so we can safely reply "xxxxxxxx" here.
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self.put_gdb_packet(b'x' * 8)
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