diff --git a/dts/arm/silabs/efm32hg.dtsi b/dts/arm/silabs/efm32hg.dtsi new file mode 100644 index 00000000000..2033291a9b1 --- /dev/null +++ b/dts/arm/silabs/efm32hg.dtsi @@ -0,0 +1,106 @@ +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m0+"; + reg = <0>; + }; + }; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + }; + + soc { + uart0: uart@4000c000 { /* USART0 */ + compatible = "silabs,efm32-usart"; + reg = <0x4000c000 0x400>; + interrupts = <17 0 18 0>; + status = "disabled"; + label = "UART_0"; + }; + + uart1: uart@4000c400 { /* USART1 */ + compatible = "silabs,efm32-usart"; + reg = <0x4000c400 0x400>; + interrupts = <8 0 9 0>; + status = "disabled"; + label = "UART_1"; + }; + + gpio@40006100 { + compatible = "silabs,efm32-gpio"; + reg = <0x40006100 0xf00>; + interrupts = <1 0 6 0>; + interrupt-names = "GPIO_EVEN", "GPIO_ODD"; + label = "GPIO"; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@40006000 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40006000 0x24>; + label = "GPIO_A"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiob: gpio@40006024 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40006024 0x24>; + label = "GPIO_B"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioc: gpio@40006048 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40006048 0x24>; + label = "GPIO_C"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiod: gpio@4000606c { + compatible = "silabs,efm32-gpio-port"; + reg = <0x4000606c 0x24>; + label = "GPIO_D"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioe: gpio@40006090 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40006090 0x24>; + label = "GPIO_E"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiof: gpio@400060b4 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x400060b4 0x24>; + label = "GPIO_F"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/dts/arm/silabs/efm32hg322f64.dtsi b/dts/arm/silabs/efm32hg322f64.dtsi new file mode 100644 index 00000000000..974eee4ebd1 --- /dev/null +++ b/dts/arm/silabs/efm32hg322f64.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018 Christian Taedcke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash0: flash@0 { + reg = <0 DT_SIZE_K(64)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(8)>; + }; +}; diff --git a/soc/arm/silabs_exx32/Kconfig b/soc/arm/silabs_exx32/Kconfig index cf2046699ce..fc4a4c1cdc2 100644 --- a/soc/arm/silabs_exx32/Kconfig +++ b/soc/arm/silabs_exx32/Kconfig @@ -19,6 +19,7 @@ config SOC_PART_NUMBER string default SOC_PART_NUMBER_EXX32_EFM32WG if SOC_SERIES_EFM32WG default SOC_PART_NUMBER_EXX32_EFR32FG1P if SOC_SERIES_EFR32FG1P + default SOC_PART_NUMBER_EXX32_EFM32HG if SOC_SERIES_EFM32HG help This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.efm32hg b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.efm32hg new file mode 100644 index 00000000000..8e28faedfc2 --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.efm32hg @@ -0,0 +1,32 @@ +# Kconfig - Silicon Labs EFM32HG-SLSTK3400A platform configuration options + +# +# Copyright (c) 2018 Marcio Montenegro +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_EFM32HG + +config SOC + string + default "efm32hg" + +config GPIO + def_bool y + +if GPIO + +config GPIO_GECKO + def_bool y + +endif # GPIO + +if SERIAL + +config UART_GECKO + def_bool y + +endif # SERIAL + +endif # SOC_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series new file mode 100644 index 00000000000..163a7fb6741 --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series @@ -0,0 +1,21 @@ +# Kconfig - EFM32HG series configuration options +# +# Copyright (c) 2018 Christian Taedcke +# Copyright (c) 2018 Marcio Montenegro +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_EFM32HG + +config SOC_SERIES + default "efm32hg" + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 20 + +source "soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.e*" + +endif # SOC_SERIES_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.series b/soc/arm/silabs_exx32/efm32hg/Kconfig.series new file mode 100644 index 00000000000..56dfc5a7e8d --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/Kconfig.series @@ -0,0 +1,16 @@ +# Kconfig - EFM32HG MCU line +# +# Copyright (c) 2018 Marcio Montenegro +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_EFM32HG + bool "EFM32HG Series MCU" + select CPU_CORTEX_M + select CPU_CORTEX_M0PLUS + select SOC_FAMILY_EXX32 + select SYS_POWER_LOW_POWER_STATE_SUPPORTED + select CPU_HAS_SYSTICK + help + Enable support for EFM32 Happy Gecko MCU series diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.soc b/soc/arm/silabs_exx32/efm32hg/Kconfig.soc new file mode 100644 index 00000000000..5797b69cab4 --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/Kconfig.soc @@ -0,0 +1,32 @@ +# Kconfig - EFM32HG MCU line +# +# Copyright (c) 2018 Marcio Montenegro +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice +prompt "EFM32 Happy Gecko MCU Selection" +depends on SOC_SERIES_EFM32HG + +config SOC_EFM32HG + bool "SOC_EFM32HG" + select HAS_SILABS_GECKO + select HAS_CMU + +endchoice + +if SOC_SERIES_EFM32HG + +config SOC_PART_NUMBER_EFM32HG322F64 + bool + +config SOC_PART_NUMBER_EXX32_EFM32HG + string + default "EFM32HG322F64" if SOC_PART_NUMBER_EFM32HG322F64 + help + This string holds the full part number of the SoC. It is a hidden option + that you should not set directly. The part number selection choice defines + the default value for this string. + +endif # SOC_SERIES_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h new file mode 100644 index 00000000000..2fe989a3121 --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h @@ -0,0 +1,28 @@ +/* This file is a temporary workaround for mapping of the generated information + * to the current driver definitions. This will be removed when the drivers + * are modified to handle the generated information, or the mapping of + * generated data matches the driver definitions. + */ + +/* SoC level DTS fixup file */ + +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_UART_GECKO_0_NAME SILABS_EFM32_USART_4000C000_LABEL + +#define CONFIG_UART_GECKO_0_BAUD_RATE SILABS_EFM32_USART_4000C000_CURRENT_SPEED +#define CONFIG_UART_GECKO_0_IRQ_PRI SILABS_EFM32_USART_4000C000_IRQ_0_PRIORITY + +#define CONFIG_GPIO_GECKO_COMMON_NAME SILABS_EFM32_GPIO_40006100_LABEL +#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN +#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY +#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD +#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY + +#define CONFIG_GPIO_GECKO_PORTA_NAME SILABS_EFM32_GPIO_PORT_40006000_LABEL +#define CONFIG_GPIO_GECKO_PORTB_NAME SILABS_EFM32_GPIO_PORT_40006024_LABEL +#define CONFIG_GPIO_GECKO_PORTC_NAME SILABS_EFM32_GPIO_PORT_40006048_LABEL +#define CONFIG_GPIO_GECKO_PORTD_NAME SILABS_EFM32_GPIO_PORT_4000606C_LABEL +#define CONFIG_GPIO_GECKO_PORTE_NAME SILABS_EFM32_GPIO_PORT_40006090_LABEL +#define CONFIG_GPIO_GECKO_PORTF_NAME SILABS_EFM32_GPIO_PORT_400060B4_LABEL + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arm/silabs_exx32/efm32hg/linker.ld b/soc/arm/silabs_exx32/efm32hg/linker.ld new file mode 100644 index 00000000000..755234d6777 --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/linker.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018 Marcio Montenegro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * This is the linker script for both standard images. + */ + +#include + +#include diff --git a/soc/arm/silabs_exx32/efm32hg/soc.h b/soc/arm/silabs_exx32/efm32hg/soc.h new file mode 100644 index 00000000000..21677f5e5cc --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/soc.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017 Christian Taedcke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the efm32hg soc + * + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef _ASMLANGUAGE + +#include +#include + +#include "soc_pinmap.h" +#include "../common/soc_gpio.h" + +#endif /* !_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC__H_ */ diff --git a/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h b/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h new file mode 100644 index 00000000000..ea548e77fdb --- /dev/null +++ b/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2018 Marcio Montenegro + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs EFM32HG MCU pin definitions. + * + * This file contains pin configuration data required by different MCU + * modules to correctly configure GPIO controller. + */ + +#ifndef _SILABS_EFM32HG_SOC_PINMAP_H_ +#define _SILABS_EFM32HG_SOC_PINMAP_H_ + +#include +#include + +#ifdef CONFIG_SOC_PART_NUMBER_EFM32HG322F64 +#ifdef CONFIG_USART_GECKO_0 +#if (CONFIG_USART_GECKO_0_GPIO_LOC == 0) +#define PIN_USART0_TXD {gpioPortE, 10, gpioModePushPull, 1} +#define PIN_USART0_RXD {gpioPortE, 11, gpioModeInput, 1} +#elif (CONFIG_USART_GECKO_0_GPIO_LOC == 3) +#define PIN_USART0_TXD {gpioPortE, 13, gpioModePushPull, 1} +#define PIN_USART0_RXD {gpioPortE, 12, gpioModeInput, 1} +#elif (CONFIG_USART_GECKO_0_GPIO_LOC == 4) +#define PIN_USART0_TXD {gpioPortB, 7, gpioModePushPull, 1} +#define PIN_USART0_RXD {gpioPortB, 8, gpioModeInput, 1} +#elif (CONFIG_USART_GECKO_0_GPIO_LOC == 5) || \ + (CONFIG_USART_GECKO_0_GPIO_LOC == 6) +#define PIN_USART0_TXD {gpioPortC, 0, gpioModePushPull, 1} +#define PIN_USART0_RXD {gpioPortC, 1, gpioModeInput, 1} +#else +#error ("Serial Driver for Gecko MCUs not implemented for this location index") +#endif +#endif /* CONFIG_USART_GECKO_0 */ + +#ifdef CONFIG_USART_GECKO_1 +#if (CONFIG_USART_GECKO_1_GPIO_LOC == 0) +#define PIN_USART1_TXD {gpioPortC, 0, gpioModePushPull, 1} +#define PIN_USART1_RXD {gpioPortC, 1, gpioModeInput, 1} +#elif (CONFIG_USART_GECKO_1_GPIO_LOC == 2) || \ + (CONFIG_USART_GECKO_1_GPIO_LOC == 3) +#define PIN_USART1_TXD {gpioPortD, 7, gpioModePushPull, 1} +#define PIN_USART1_RXD {gpioPortD, 6, gpioModeInput, 1} +#elif (CONFIG_USART_GECKO_1_GPIO_LOC == 4) +#define PIN_USART1_TXD {gpioPortF, 2, gpioModePushPull, 1} +#define PIN_USART1_RXD {gpioPortA, 0, gpioModeInput, 1} +#elif (CONFIG_USART_GECKO_1_GPIO_LOC == 5) +#define PIN_USART1_TXD {gpioPortC, 1, gpioModePushPull, 1} +#define PIN_USART1_RXD {gpioPortC, 2, gpioModeInput, 1} +#else +#error ("Serial Driver for Gecko MCUs not implemented for this location index") +#endif +#endif /* CONFIG_USART_GECKO_1 */ +#else +#error ("Pinmap not available for this for Happy Gecko MCU") +#endif /* SOC_PART_NUMBER_EFM32HG322F64*/ + +#endif /* _SILABS_EFM32HG_SOC_PINMAP_H_ */