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soc: amd: acp_6_0: add support for AMD ACP_6_0 soc.

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Add a common part for AMD board ACP_6_0_ADSP.

Add support for ACP_6_0_ADSP BOARD,
which represents ACP_6_0 soc.

This has a 1 Xtensa HiFi5 core, with 200-800MHz
1.75 MB HP SRAM / 512 KB IRAM/DRAM,
1 x SP (I2S, PCM), 1 x BT (I2S, PCM), 1 x HS(I2S, PCM), DMIC as
audio interfaces.

Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
This commit is contained in:
DineshKumar Kalva 2024-10-14 15:02:35 +05:30 • committed by Anas Nashif
commit 173cc387a0
12 changed files with 1049 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

15
soc/amd/acp_6_0/CMakeLists.txt Normal file
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if(CONFIG_SOC_ACP_6_0)
zephyr_include_directories(adsp)
add_subdirectory(adsp)
# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
add_custom_target(zephyr.ri ALL
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
)
add_custom_command(
OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
COMMENT "west sign --if-tool-available --tool rimage ..."
COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
endif()

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soc/amd/acp_6_0/Kconfig Normal file
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# Copyright 2024 AMD
# SPDX-License-Identifier: Apache-2.0
config SOC_ACP_6_0
select XTENSA
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
select XTENSA_RESET_VECTOR
select ATOMIC_OPERATIONS_BUILTIN

28
soc/amd/acp_6_0/Kconfig.defconfig Normal file
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# Copyright (c) 2024 AMD
# SPDX-License-Identifier: Apache-2.0
if SOC_ACP_6_0
config DCACHE_LINE_SIZE
default 128
config CACHE_MANAGEMENT
default n
config XTENSA_TIMER
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 600000000 if XTENSA_TIMER
config KERNEL_ENTRY
default "__start"
config MULTI_LEVEL_INTERRUPTS
default n
config 2ND_LEVEL_INTERRUPTS
default n
config KERNEL_ENTRY
default "__start"
endif

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soc/amd/acp_6_0/Kconfig.soc Normal file
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# Copyright (c) 2024 AMD
# SPDX-License-Identifier: Apache-2.0
config SOC_ACP_6_0
bool
default "BOARD_ACP_6_0_ADSP"
config SOC
default "acp_6_0" if SOC_ACP_6_0
config SOC_TOOLCHAIN_NAME
string
default "amd_acp_6_0_adsp"

4
soc/amd/acp_6_0/adsp/CMakeLists.txt Normal file
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# Copyright (c) 2024 AMD
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(include)

165
soc/amd/acp_6_0/adsp/_soc_inthandlers.h Normal file
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/*
* Copyright (c) 2024 AMD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged interrupt, in numerical
* order (low bits first) and will return a mask of that bit that can
* then be cleared by the calling code. Unrecognized bits for the
* level will invoke an error handler.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/sys/util.h>
#include <zephyr/sw_isr_table.h>
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 4
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 5
#error core-isa.h interrupt level does not match dispatcher!
#endif
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 7
#error core-isa.h interrupt level does not match dispatcher!
#endif
static inline int _xtensa_handle_one_int1(unsigned int mask)
{
int irq;
if (mask & 0x3) {
if (mask & BIT(0)) {
mask = BIT(0);
irq = 0;
goto handle_irq;
}
if (mask & BIT(1)) {
mask = BIT(1);
irq = 1;
goto handle_irq;
}
} else {
if (mask & BIT(6)) {
mask = BIT(6);
irq = 6;
goto handle_irq;
}
if (mask & BIT(8)) {
mask = BIT(8);
irq = 8;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int2(unsigned int mask)
{
int irq;
if (mask & BIT(2)) {
mask = BIT(2);
irq = 2;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int3(unsigned int mask)
{
int irq;
if (mask & BIT(3)) {
mask = BIT(3);
irq = 3;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int4(unsigned int mask)
{
int irq;
if (mask & BIT(4)) {
mask = BIT(4);
irq = 4;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int5(unsigned int mask)
{
int irq;
if (mask & BIT(5)) {
mask = BIT(5);
irq = 5;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int7(unsigned int mask)
{
int irq;
if (mask & BIT(7)) {
mask = BIT(7);
irq = 7;
goto handle_irq;
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
return mask;
}
static inline int _xtensa_handle_one_int0(unsigned int mask)
{
return 0;
}
static inline int _xtensa_handle_one_int6(unsigned int mask)
{
return 0;
}

10
soc/amd/acp_6_0/adsp/include/adsp/cache.h Normal file
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/*
* Copyright (c) 2024 AMD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __COMMON_ADSP_CACHE_H__
#define __COMMON_ADSP_CACHE_H__
#include <xtensa/hal.h>
#endif

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soc/amd/acp_6_0/adsp/include/adsp/io.h Normal file
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/*
* Copyright (c) 2024 AMD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __INCLUDE_IO__
#define __INCLUDE_IO__
#include <stdint.h>
#include <soc/memory.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/arch/common/sys_io.h>
static inline uint32_t io_reg_read(uint32_t reg)
{
return sys_read32(reg);
}
static inline void io_reg_write(uint32_t reg, uint32_t val)
{
sys_write32(val, reg);
}
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
{
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
}
static inline uint16_t io_reg_read16(uint32_t reg)
{
return sys_read16(reg);
}
static inline void io_reg_write16(uint32_t reg, uint16_t val)
{
sys_write16(val, reg);
}
#endif

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soc/amd/acp_6_0/adsp/linker.ld Normal file
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/*
* Copyright (c) 2022,2024 AMD
* SPDX-License-Identifier: Apache-2.0
*/
/*
* @file
* @brief Linker command/script file
*
* Linker script for the AMD acp_6_0 platform
*/
OUTPUT_ARCH(xtensa)
#include <zephyr/devicetree.h>
#include <xtensa/config/core-isa.h>
#include <memory.h>
#include <zephyr/linker/sections.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
PROVIDE(__memctl_default = 0x00000000);
PROVIDE(_MemErrorHandler = 0x00000000);
#define RAMABLE_REGION sdram0 :sdram0_phdr
#define ROMABLE_REGION sdram0 :sdram0_phdr
MEMORY
{
vector_reset_text :
org = XCHAL_RESET_VECTOR_PADDR_IRAM,
len = MEM_RESET_TEXT_SIZE
vector_reset_lit :
org = XCHAL_RESET_VECTOR_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
len = MEM_RESET_LIT_SIZE
vector_base_text :
org = XCHAL_WINDOW_VECTORS_PADDR_IRAM, //XCHAL_VECBASE_RESET_PADDR,
len = MEM_VECBASE_LIT_SIZE
vector_int2_lit :
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int2_text :
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_int3_lit :
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int3_text :
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_int4_lit :
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int4_text :
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_int5_lit :
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int5_text :
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_int6_lit :
org = XCHAL_INTLEVEL6_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int6_text :
org = XCHAL_INTLEVEL6_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_int7_lit :
org = XCHAL_INTLEVEL7_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_int7_text :
org = XCHAL_INTLEVEL7_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_kernel_lit :
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_kernel_text :
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_user_lit :
org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_user_text :
org = XCHAL_USER_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
vector_double_lit :
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
len = MEM_VECT_LIT_SIZE
vector_double_text :
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
len = MEM_VECT_TEXT_SIZE
iram_text_start :
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE)
sdram0 :
org = DRAM0_BASE,
len = DRAM0_SIZE
sdram1 :
org = SRAM1_BASE,
len = SRAM1_SIZE
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST :
org = IDT_BASE,
len = IDT_SIZE
#endif
static_uuid_entries_seg (!ari) :
org = UUID_ENTRY_ELF_BASE,
len = UUID_ENTRY_ELF_SIZE
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
}
PHDRS
{
vector_reset_text_phdr PT_LOAD;
vector_reset_lit_phdr PT_LOAD;
vector_base_text_phdr PT_LOAD;
vector_base_lit_phdr PT_LOAD;
vector_int2_text_phdr PT_LOAD;
vector_int2_lit_phdr PT_LOAD;
vector_int3_text_phdr PT_LOAD;
vector_int3_lit_phdr PT_LOAD;
vector_int4_text_phdr PT_LOAD;
vector_int4_lit_phdr PT_LOAD;
vector_int5_text_phdr PT_LOAD;
vector_int5_lit_phdr PT_LOAD;
vector_int6_text_phdr PT_LOAD;
vector_int6_lit_phdr PT_LOAD;
vector_int7_text_phdr PT_LOAD;
vector_int7_lit_phdr PT_LOAD;
vector_kernel_text_phdr PT_LOAD;
vector_kernel_lit_phdr PT_LOAD;
vector_user_text_phdr PT_LOAD;
vector_user_lit_phdr PT_LOAD;
vector_double_text_phdr PT_LOAD;
vector_double_lit_phdr PT_LOAD;
iram_text_start_phdr PT_LOAD;
sdram0_phdr PT_LOAD;
sdram1_phdr PT_LOAD;
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
}
/* Default entry point: */
/*ENTRY(_ResetVector)*/
_rom_store_table = 0;
/* ABI0 does not use Window base */
PROVIDE(_memmap_vecbase_reset = XCHAL_WINDOW_VECTORS_PADDR);
ENTRY(CONFIG_KERNEL_ENTRY)
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
_memmap_cacheattr_wt_base = 0x11021000;
_memmap_cacheattr_bp_base = 0x22022000;
_memmap_cacheattr_unused_mask = 0x00F00FFF;
_memmap_cacheattr_wb_trapnull = 0x4422422F;
_memmap_cacheattr_wba_trapnull = 0x4422422F;
_memmap_cacheattr_wbna_trapnull = 0x25222222;
_memmap_cacheattr_wt_trapnull = 0x1122122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0x44F24FFF;
_memmap_cacheattr_wt_strict = 0x11F21FFF;
_memmap_cacheattr_bp_strict = 0x22F22FFF;
_memmap_cacheattr_wb_allvalid = 0x44224222;
_memmap_cacheattr_wt_allvalid = 0x11221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
SECTIONS
{
#include <zephyr/linker/rel-sections.ld>
#ifdef CONFIG_LLEXT
#include <zephyr/linker/llext-sections.ld>
#endif
.ResetVector.text : ALIGN(4)
{
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
} >vector_reset_text :vector_reset_text_phdr
.ResetVector.literal : ALIGN(4)
{
_ResetVector_literal_start = ABSOLUTE(.);
*(.ResetVector.literal)
_ResetVector_literal_end = ABSOLUTE(.);
} >vector_reset_lit :vector_reset_lit_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
} >vector_base_text :vector_base_text_phdr
.Level2InterruptVector.literal : ALIGN(4)
{
_Level2InterruptVector_literal_start = ABSOLUTE(.);
*(.Level2InterruptVector.literal)
_Level2InterruptVector_literal_end = ABSOLUTE(.);
} >vector_int2_lit :vector_int2_lit_phdr
.Level2InterruptVector.text : ALIGN(4)
{
_Level2InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level2InterruptVector.text))
_Level2InterruptVector_text_end = ABSOLUTE(.);
} >vector_int2_text :vector_int2_text_phdr
.Level3InterruptVector.literal : ALIGN(4)
{
_Level3InterruptVector_literal_start = ABSOLUTE(.);
*(.Level3InterruptVector.literal)
_Level3InterruptVector_literal_end = ABSOLUTE(.);
} >vector_int3_lit :vector_int3_lit_phdr
.Level3InterruptVector.text : ALIGN(4)
{
_Level3InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level3InterruptVector.text))
_Level3InterruptVector_text_end = ABSOLUTE(.);
} >vector_int3_text :vector_int3_text_phdr
.Level4InterruptVector.literal : ALIGN(4)
{
_Level4InterruptVector_literal_start = ABSOLUTE(.);
*(.Level4InterruptVector.literal)
_Level4InterruptVector_literal_end = ABSOLUTE(.);
} >vector_int4_lit :vector_int4_lit_phdr
.Level4InterruptVector.text : ALIGN(4)
{
_Level4InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level4InterruptVector.text))
_Level4InterruptVector_text_end = ABSOLUTE(.);
} >vector_int4_text :vector_int4_text_phdr
.Level5InterruptVector.literal : ALIGN(4)
{
_Level5InterruptVector_literal_start = ABSOLUTE(.);
*(.Level5InterruptVector.literal)
_Level5InterruptVector_literal_end = ABSOLUTE(.);
} >vector_int5_lit :vector_int5_lit_phdr
.Level5InterruptVector.text : ALIGN(4)
{
_Level5InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level5InterruptVector.text))
_Level5InterruptVector_text_end = ABSOLUTE(.);
} >vector_int5_text :vector_int5_text_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
} >vector_int6_lit :vector_int6_lit_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
} >vector_int6_text :vector_int6_text_phdr
.NMIExceptionVector.literal : ALIGN(4)
{
_NMIExceptionVector_literal_start = ABSOLUTE(.);
*(.NMIExceptionVector.literal)
_NMIExceptionVector_literal_end = ABSOLUTE(.);
} >vector_int7_lit :vector_int5_lit_phdr
.NMIExceptionVector.text : ALIGN(4)
{
_NMIExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.NMIExceptionVector.text))
_NMIExceptionVector_text_end = ABSOLUTE(.);
} >vector_int7_text :vector_int5_text_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
} >vector_kernel_lit :vector_kernel_lit_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
} >vector_kernel_text :vector_kernel_text_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
} >vector_user_lit :vector_user_lit_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
} >vector_user_text :vector_user_text_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
} >vector_double_lit :vector_double_lit_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
} >vector_double_text :vector_double_text_phdr
.iram.text : ALIGN(4)
{
_stext = .;
_iram_text_start = ABSOLUTE(.);
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
_iram_text_end = ABSOLUTE(.);
} >iram_text_start :iram_text_start_phdr
/* stack */
_end = SOF_STACK_END;
PROVIDE(end = SOF_STACK_END);
_stack_sentry = SOF_STACK_END;
__stack = SOF_STACK_BASE;
.text : ALIGN(4)
{
_stext = .;
__text_region_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
*(.ResetVector.literal) /* default is _start in zephyr, set it to reset vector as in sof */
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
__text_region_end = ABSOLUTE(.);
_etext = .;
} >iram_text_start :iram_text_start_phdr
.rodata : ALIGN(4)
{
__rodata_region_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table .gcc_except_table.*))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
__rodata_region_end = ABSOLUTE(.);
} >sdram0 :sdram0_phdr
.module_init : ALIGN(4)
{
_module_init_start = ABSOLUTE(.);
*(*.initcall)
_module_init_end = ABSOLUTE(.);
} >sdram0 :sdram0_phdr
#include <zephyr/linker/common-rom.ld>
.fw_ready : ALIGN(4)
{
KEEP (*(.fw_ready))
} >sdram0 :sdram0_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sdram0 :sdram0_phdr
.data : ALIGN(4)
{
__data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_trace_ctx_start = ABSOLUTE(.);
*(.trace_ctx)
_trace_ctx_end = ABSOLUTE(.);
. = ALIGN(4);
*(.gna_model)
__data_end = ABSOLUTE(.);
. = ALIGN(4096);
} >sdram0 :sdram0_phdr
.lit4 : ALIGN(4)
{
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
} >sdram0 :sdram0_phdr
#include <zephyr/linker/common-ram.ld>
/* Located in generated directory. This file is populated by calling
* zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
*/
#include <snippets-rom-sections.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >sdram0 :sdram0_phdr
.heap_mem (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_heap_mem_start = ABSOLUTE(.);
*(*.heap_mem)
_heap_mem_end = ABSOLUTE(.);
} >sdram1 :sdram1_phdr
/* stack */
_end = ALIGN (8);
PROVIDE(end = ALIGN (8));
__stack = DRAM0_BASE + DRAM0_SIZE;
.comment 0 : { *(.comment) } /* stack */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.xt.profile_range 0 :
{
KEEP (*(.xt.profile_range))
KEEP (*(.gnu.linkonce.profile_range.*))
}
.xt.profile_ranges 0 :
{
KEEP (*(.xt.profile_ranges))
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
}
.xt.profile_files 0 :
{
KEEP (*(.xt.profile_files))
KEEP (*(.gnu.linkonce.xt.profile_files.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <zephyr/linker/intlist.ld>
#endif
.static_uuid_entries (COPY) : ALIGN(1024)
{
*(*.static_uuids)
} > static_uuid_entries_seg :static_uuid_entries_phdr
.static_log_entries (COPY) : ALIGN(1024)
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr
.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
/DISCARD/ : { *(.note.GNU-stack) }
}

160
soc/amd/acp_6_0/adsp/memory.h Normal file
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@ -0,0 +1,160 @@
/*
* Copyright(c) 2022 AMD
* SPDX-License-Identifier: Apache-2.0
*
* Author: Basavaraj Hiregoudar <basavaraj.hiregoudar@amd.com>
* DineshKumar Kalva <dineshkumar.kalva@amd.com>
*/
#ifndef ZEPHYR_SOC_AMD_ADSP_MEMORY_H_
#define ZEPHYR_SOC_AMD_ADSP_MEMORY_H_
#define PLATFORM_CORE_COUNT 1
#define PLATFORM_PRIMARY_CORE_ID 0
#define IRAM_BASE 0x7F000000
#define IRAM_SIZE 0x60000
#define IRAM_RESERVE_HEADER_SPACE 0x400
#define MEM_RESET_TEXT_SIZE 0x400
#define MEM_RESET_LIT_SIZE 0x8
#define XCHAL_RESET_VECTOR_PADDR_IRAM 0x7F000000
#define XCHAL_WINDOW_VECTORS_PADDR_IRAM 0x7F000400
#define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
#define MEM_VECBASE_LIT_SIZE 0x178
#define MEM_WIN_TEXT_SIZE 0x178
/* Vector and literal sizes - not in core-isa.h */
#define MEM_VECT_LIT_SIZE 0x7
#define MEM_VECT_TEXT_SIZE 0x37
#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x180)
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1C0)
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x200)
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x240)
#define XCHAL_INTLEVEL6_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x280)
#define XCHAL_INTLEVEL7_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x2C0)
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x300)
#define XCHAL_USER_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x340)
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x3C0)
/* Location for the intList section which is later used to construct the
* Interrupt Descriptor Table (IDT). This is a bogus address as this
* section will be stripped off in the final image.
*/
#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
/* size of the Interrupt Descriptor Table (IDT) */
#define IDT_SIZE 0x2000
/* physical DSP addresses */
#define IRAM_BASE 0x7F000000
#define IRAM_SIZE 0x60000 /* 384K */
#define SRAM0_BASE 0x9FF00000 /* Scratch mem */
#define SRAM1_BASE 0x60006000
#define SRAM1_SIZE 0x80000 /* 256K Data Mem */
#define DRAM0_BASE 0xE0000000
#define DRAM0_SIZE 0x20000 /* 128K ,to use for heap mem */
#define DMA0_BASE PU_REGISTER_BASE
#define DMA0_SIZE 0x4
#define PU_REGISTER_BASE (0x9FD00000 - 0x01240000)
#define ACP_I2S_RX_RINGBUFADDR 0x1242000
/* DAI DMA register base address */
#define DAI_BASE (PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR)
#define DAI_BASE_REM (PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFADDR)
#define DAI_SIZE 0x4
#define BT_TX_FIFO_OFFST (ACP_P1_BT_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
#define BT_RX_FIFO_OFFST (ACP_P1_BT_RX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
#define HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
#define HS_RX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
#define UUID_ENTRY_ELF_BASE 0x1FFFA000
#define UUID_ENTRY_ELF_SIZE \
0x6000 /* Log buffer base need to be updated properly, these are used in linker scripts \
*/
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000 /* Stack configuration */
#define SOF_STACK_SIZE 0x1000
#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE
#define SOF_STACK_END (DRAM0_BASE + DRAM0_SIZE)
#define SOF_STACK_BASE (SOF_STACK_END + SOF_STACK_SIZE) /* Mailbox configuration */
#define SRAM_OUTBOX_BASE SRAM0_BASE
#define SRAM_OUTBOX_SIZE 0x400
#define SRAM_OUTBOX_OFFSET 0
#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
#define SRAM_INBOX_SIZE 0x400
#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
#define SRAM_DEBUG_SIZE 0x400
#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
#define SRAM_EXCEPT_SIZE 0x400
#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
#define SRAM_STREAM_SIZE 0x400
#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
#define SRAM_TRACE_SIZE 0x400
#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
#define SOF_MAILBOX_SIZE \
(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \
SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
/* Heap section sizes for module pool */
#define HEAP_RT_COUNT8 0
#define HEAP_RT_COUNT16 48
#define HEAP_RT_COUNT32 48
#define HEAP_RT_COUNT64 32
#define HEAP_RT_COUNT128 60
#define HEAP_RT_COUNT256 32
#define HEAP_RT_COUNT512 4
#define HEAP_RT_COUNT1024 12
#define HEAP_RT_COUNT2048 12
/* Heap section sizes for system runtime heap */
#define HEAP_SYS_RT_COUNT64 64
#define HEAP_SYS_RT_COUNT512 20 /*rembrandt-arch*/
#define HEAP_SYS_RT_COUNT1024 6
/* Heap configuration */
#define HEAP_SYSTEM_BASE DRAM0_BASE /* SRAM1_BASE */
#define HEAP_SYSTEM_SIZE 0xE000
#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE
#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
#define HEAP_SYS_RUNTIME_SIZE \
(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024)
#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
#define HEAP_RUNTIME_SIZE \
(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \
HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048)
#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
#define HEAP_BUFFER_SIZE (0xF000)
#define HEAP_BUFFER_BLOCK_SIZE 0x180
#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
#define PLATFORM_HEAP_SYSTEM 1
#define PLATFORM_HEAP_SYSTEM_RUNTIME 1
#define PLATFORM_HEAP_RUNTIME 1
#define PLATFORM_HEAP_BUFFER 1
/* Vector and literal sizes - not in core-isa.h */
#define SOF_MEM_VECT_LIT_SIZE 0x7
#define SOF_MEM_VECT_TEXT_SIZE 0x37
#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
#define SOF_MEM_RESET_TEXT_SIZE 0x400
#define SOF_MEM_RESET_LIT_SIZE 0x8
#define SOF_MEM_VECBASE_LIT_SIZE 0x178
#define SOF_MEM_WIN_TEXT_SIZE 0x178
#define SOF_MEM_RO_SIZE 0x8
#define uncache_to_cache(address) address
#define cache_to_uncache(address) address
#define is_uncached(address) 0
#define HEAP_BUF_ALIGNMENT PLATFORM_DCACHE_ALIGN
/* brief EDF task's default stack size in bytes */
#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072
#endif /* ZEPHYR_SOC_AMD_ADSP_MEMORY_H_ */

2
soc/amd/acp_6_0/soc.yml Normal file
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@ -0,0 +1,2 @@
socs:
- name: acp_6_0