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soc: intel_adsp: lpsram init refactor

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This patch contains small refactor of lpsram init function (defines
registers and adds new macro).

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit is contained in:
Tomasz Leman 2023-10-13 21:43:05 +02:00 • committed by Carles Cufí
commit 16f729214b
3 changed files with 38 additions and 4 deletions
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18
soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h
View file

@ -147,6 +147,17 @@ struct ace_hpsram_regs {
uint8_t HSxPGISTS; uint8_t HSxPGISTS;
uint8_t reserved1[3]; uint8_t reserved1[3];
}; };
struct ace_lpsram_regs {
/** @brief power gating control */
uint8_t USxPGCTL;
/** @brief retention mode control */
uint8_t USxRMCTL;
uint8_t reserved[2];
/** @brief power gating status */
uint8_t USxPGISTS;
uint8_t reserved1[3];
};
#endif #endif
/* These registers are for the L2 HP SRAM bank power management control and status.*/ /* These registers are for the L2 HP SRAM bank power management control and status.*/
@ -156,4 +167,11 @@ struct ace_hpsram_regs {
#define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \ #define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \
(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx))) (L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))
/* These registers are for the L2 LP SRAM bank power management control and status.*/
#define L2LSBPM_REG 0x71D80
#define L2LSBPM_REG_SIZE 0x0008
#define LPSRAM_REGS(block_idx) ((volatile struct ace_lpsram_regs *const) \
(L2LSBPM_REG + L2LSBPM_REG_SIZE * (block_idx)))
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */ #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

18
soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h
View file

@ -145,6 +145,17 @@ struct ace_hpsram_regs {
uint8_t HSxPGISTS; uint8_t HSxPGISTS;
uint8_t reserved1[3]; uint8_t reserved1[3];
}; };
struct ace_lpsram_regs {
/** @brief power gating control */
uint8_t USxPGCTL;
/** @brief retention mode control */
uint8_t USxRMCTL;
uint8_t reserved[2];
/** @brief power gating status */
uint8_t USxPGISTS;
uint8_t reserved1[3];
};
#endif #endif
/* These registers are for the L2 HP SRAM bank power management control and status.*/ /* These registers are for the L2 HP SRAM bank power management control and status.*/
@ -154,4 +165,11 @@ struct ace_hpsram_regs {
#define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \ #define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \
(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx))) (L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))
/* These registers are for the L2 LP SRAM bank power management control and status.*/
#define L2LSBPM_REG 0x71D80
#define L2LSBPM_REG_SIZE 0x0008
#define LPSRAM_REGS(block_idx) ((volatile struct ace_lpsram_regs *const) \
(L2LSBPM_REG + L2LSBPM_REG_SIZE * (block_idx)))
#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */ #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */

6
soc/xtensa/intel_adsp/ace/sram.c
View file

@ -36,15 +36,13 @@ __imr void hp_sram_init(uint32_t memory_size)
__imr void lp_sram_init(void) __imr void lp_sram_init(void)
{ {
uint32_t lpsram_ebb_quantity = ace_lpsram_get_bank_count(); uint32_t lpsram_ebb_quantity = ace_lpsram_get_bank_count();
volatile uint32_t *l2usbpmptr = (volatile uint32_t *)ACE_L2MM->l2usbpmptr;
volatile uint8_t *status = (volatile uint8_t *)l2usbpmptr + 4;
uint32_t idx; uint32_t idx;
for (idx = 0; idx < lpsram_ebb_quantity; ++idx) { for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
*(l2usbpmptr + idx * 2) = 0; LPSRAM_REGS(idx)->USxPGCTL = 0;
} }
for (idx = 0; idx < lpsram_ebb_quantity; ++idx) { for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
while (*(status + idx * 8) != 0) { while (LPSRAM_REGS(idx)->USxPGISTS != 0) {
} }
} }