From 168395f1953ca5c4c43655de11dacf4f8ccd3cec Mon Sep 17 00:00:00 2001
From: Sercan Erat <sercanerat@gmail.com>
Date: Mon, 12 May 2025 00:19:58 +0300
Subject: [PATCH] boards: rakwireless: rak3172: Fix clock settings

Enabling HSE and LSE clock settings.

Signed-off-by: Sercan Erat <sercanerat@gmail.com>
---
 boards/rakwireless/rak3172/rak3172.dts | 16 ++++------------
 dts/arm/rakwireless/rak3172.dtsi       |  2 ++
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/boards/rakwireless/rak3172/rak3172.dts b/boards/rakwireless/rak3172/rak3172.dts
index 936ac3b89a0..7685fa66af0 100644
--- a/boards/rakwireless/rak3172/rak3172.dts
+++ b/boards/rakwireless/rak3172/rak3172.dts
@@ -43,20 +43,16 @@
 
 &lptim1 {
 	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
-		 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
-	status = "okay";
-};
-
-&clk_lsi {
+		 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
 	status = "okay";
 };
 
 &pll {
 	div-m = <1>;
-	mul-n = <6>;
+	mul-n = <3>;
 	div-r = <2>;
 	div-q = <2>;
-	clocks = <&clk_hsi>;
+	clocks = <&clk_hse>;
 	status = "okay";
 };
 
@@ -99,7 +95,7 @@
 
 &rtc {
 	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
-		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+		 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
 	status = "okay";
 };
 
@@ -115,10 +111,6 @@
 	status = "okay";
 };
 
-&clk_hsi {
-	status = "okay";
-};
-
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
diff --git a/dts/arm/rakwireless/rak3172.dtsi b/dts/arm/rakwireless/rak3172.dtsi
index 4e3a0a2abdc..15527695960 100644
--- a/dts/arm/rakwireless/rak3172.dtsi
+++ b/dts/arm/rakwireless/rak3172.dtsi
@@ -7,10 +7,12 @@
 #include <st/wl/stm32wle5ccux-pinctrl.dtsi>
 
 &clk_hse {
+	status = "okay";
 	clock-frequency = <DT_FREQ_M(32)>;
 };
 
 &clk_lse {
+	status = "okay";
 	clock-frequency = <32768>;
 };