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soc: renesas: ra2l1: Add initial support for Renesas RA2L1 SOC series

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Add basic support for Renesas RA2L1 SOC series.

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
This commit is contained in:
Thao Luong 2025-01-14 23:15:32 +07:00 • committed by Fabio Baltieri
commit 168284a8cc
13 changed files with 611 additions and 0 deletions
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15
soc/renesas/ra/ra2l1/CMakeLists.txt Normal file
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# Copyright (c) 2022-2024 MUNIC SA
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)
zephyr_linker_sources(ROM_START opt_set_mem.ld)
zephyr_linker_sources(SECTIONS sections.ld)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

14
soc/renesas/ra/ra2l1/Kconfig Normal file
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# Copyright (c) 2024 MUNIC SA
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA2L1
select ARM
select CPU_CORTEX_M23
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CPU_CORTEX_M_HAS_VTOR
select CPU_CORTEX_M_HAS_SYSTICK
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select HAS_SWO
select SOC_EARLY_INIT_HOOK

20
soc/renesas/ra/ra2l1/Kconfig.defconfig Normal file
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# Copyright (c) 2024 MUNIC SA
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_RA2L1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA2L1

21
soc/renesas/ra/ra2l1/Kconfig.soc Normal file
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# Copyright (c) 2024 MUNIC SA
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA2L1
bool
select SOC_FAMILY_RENESAS_RA
config SOC_R7FA2L1A9XXFP
bool
select SOC_SERIES_RA2L1
config SOC_R7FA2L1ABXXFP
bool
select SOC_SERIES_RA2L1
config SOC_SERIES
default "ra2l1" if SOC_SERIES_RA2L1
config SOC
default "r7fa2l1a9xxfp" if SOC_R7FA2L1A9XXFP
default "r7fa2l1abxxfp" if SOC_R7FA2L1ABXXFP

11
soc/renesas/ra/ra2l1/opt_set_mem.ld Normal file
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/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;

123
soc/renesas/ra/ra2l1/sections.ld Normal file
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/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
*(.fsp_dtc_vector_table)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
SECTION_PROLOGUE(.option_setting_ofs,,)
{
__OPTION_SETTING_OFS_Start = .;
KEEP(*(.option_setting_ofs0))
. = __OPTION_SETTING_OFS_Start + 0x04;
KEEP(*(.option_setting_ofs2))
. = __OPTION_SETTING_OFS_Start + 0x10;
KEEP(*(.option_setting_dualsel))
__OPTION_SETTING_OFS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
SECTION_PROLOGUE(.option_setting_sas,,)
{
__OPTION_SETTING_SAS_Start = .;
KEEP(*(.option_setting_sas))
__OPTION_SETTING_SAS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
SECTION_PROLOGUE(.option_setting_ns,,)
{
__OPTION_SETTING_NS_Start = .;
KEEP(*(.option_setting_ofs1))
. = __OPTION_SETTING_NS_Start + 0x04;
KEEP(*(.option_setting_ofs3))
. = __OPTION_SETTING_NS_Start + 0x10;
KEEP(*(.option_setting_banksel))
. = __OPTION_SETTING_NS_Start + 0x40;
KEEP(*(.option_setting_bps0))
. = __OPTION_SETTING_NS_Start + 0x44;
KEEP(*(.option_setting_bps1))
. = __OPTION_SETTING_NS_Start + 0x48;
KEEP(*(.option_setting_bps2))
. = __OPTION_SETTING_NS_Start + 0x4C;
KEEP(*(.option_setting_bps3))
. = __OPTION_SETTING_NS_Start + 0x60;
KEEP(*(.option_setting_pbps0))
. = __OPTION_SETTING_NS_Start + 0x64;
KEEP(*(.option_setting_pbps1))
. = __OPTION_SETTING_NS_Start + 0x68;
KEEP(*(.option_setting_pbps2))
. = __OPTION_SETTING_NS_Start + 0x6C;
KEEP(*(.option_setting_pbps3))
__OPTION_SETTING_NS_End = .;
} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
SECTION_PROLOGUE(.option_setting_s,,)
{
__OPTION_SETTING_S_Start = .;
KEEP(*(.option_setting_ofs1_sec))
. = __OPTION_SETTING_S_Start + 0x04;
KEEP(*(.option_setting_ofs3_sec))
. = __OPTION_SETTING_S_Start + 0x10;
KEEP(*(.option_setting_banksel_sec))
. = __OPTION_SETTING_S_Start + 0x40;
KEEP(*(.option_setting_bps_sec0))
. = __OPTION_SETTING_S_Start + 0x44;
KEEP(*(.option_setting_bps_sec1))
. = __OPTION_SETTING_S_Start + 0x48;
KEEP(*(.option_setting_bps_sec2))
. = __OPTION_SETTING_S_Start + 0x4C;
KEEP(*(.option_setting_bps_sec3))
. = __OPTION_SETTING_S_Start + 0x60;
KEEP(*(.option_setting_pbps_sec0))
. = __OPTION_SETTING_S_Start + 0x64;
KEEP(*(.option_setting_pbps_sec1))
. = __OPTION_SETTING_S_Start + 0x68;
KEEP(*(.option_setting_pbps_sec2))
. = __OPTION_SETTING_S_Start + 0x6C;
KEEP(*(.option_setting_pbps_sec3))
. = __OPTION_SETTING_S_Start + 0x80;
KEEP(*(.option_setting_ofs1_sel))
. = __OPTION_SETTING_S_Start + 0x84;
KEEP(*(.option_setting_ofs3_sel))
. = __OPTION_SETTING_S_Start + 0x90;
KEEP(*(.option_setting_banksel_sel))
. = __OPTION_SETTING_S_Start + 0xC0;
KEEP(*(.option_setting_bps_sel0))
. = __OPTION_SETTING_S_Start + 0xC4;
KEEP(*(.option_setting_bps_sel1))
. = __OPTION_SETTING_S_Start + 0xC8;
KEEP(*(.option_setting_bps_sel2))
. = __OPTION_SETTING_S_Start + 0xCC;
KEEP(*(.option_setting_bps_sel3))
__OPTION_SETTING_S_End = .;
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
SECTION_PROLOGUE(.id_code,,)
{
KEEP(*(.id_code*))
} GROUP_LINK_IN(ID_CODE)
#endif

41
soc/renesas/ra/ra2l1/soc.c Normal file
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/*
* Copyright (c) 2023-2024 MUNIC SA
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Renesas RA2L1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#include "bsp_cfg.h"
#include <bsp_api.h>
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
*/
void soc_early_init_hook(void)
{
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
}

17
soc/renesas/ra/ra2l1/soc.h Normal file
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/*
* Copyright (c) 2021-2024 MUNIC SA
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the Renesas RA2L1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_ */

4
soc/renesas/ra/soc.yml
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@ -4,6 +4,10 @@ family:
- name: ra2a1
socs:
- name: r7fa2a1ab3cfm
- name: ra2l1
socs:
- name: r7fa2l1a9xxfp
- name: r7fa2l1abxxfp
- name: ra4e1
socs:
- name: r7fa4e10d2cfm