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tests: drivers: clock control stm32 adc device clock setting

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Tests the ADC clock domain on the stm32g0 serie
Possible ADC clock sources are SYStem clock (default) or PLL_P.
No clock source HSI for the ADC tested here.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2024-11-07 17:58:58 +01:00 • committed by Benjamin Cabé
commit 1680887051
2 changed files with 18 additions and 4 deletions
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2
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay
View file

@ -77,6 +77,6 @@
}; };
&adc1 { &adc1 {
/* Basic test only. Don't configure domain clock. */ /* Basic test only. ADC1 domain clock is set by the board DTS : SYSCLK */
status = "okay"; status = "okay";
}; };

20
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_adc.c
View file

@ -25,18 +25,17 @@
#define PERIPHCLK_ADC RCC_PERIPHCLK_ADC12 #define PERIPHCLK_ADC RCC_PERIPHCLK_ADC12
#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED #define ADC_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define GET_ADC_SOURCE __HAL_RCC_GET_ADC12_SOURCE #define GET_ADC_SOURCE __HAL_RCC_GET_ADC12_SOURCE
#define ADC_SOURCE_SYSCLK RCC_ADC12CLKSOURCE_SYSCLK
#elif defined(__HAL_RCC_GET_ADC_SOURCE) #elif defined(__HAL_RCC_GET_ADC_SOURCE)
#define PERIPHCLK_ADC RCC_PERIPHCLK_ADC #define PERIPHCLK_ADC RCC_PERIPHCLK_ADC
#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC_IS_CLK_ENABLED #define ADC_IS_CLK_ENABLED __HAL_RCC_ADC_IS_CLK_ENABLED
#define GET_ADC_SOURCE __HAL_RCC_GET_ADC_SOURCE #define GET_ADC_SOURCE __HAL_RCC_GET_ADC_SOURCE
#define ADC_SOURCE_SYSCLK RCC_ADCCLKSOURCE_SYSCLK
#else #else
#define PERIPHCLK_ADC (-1) #define PERIPHCLK_ADC (-1)
#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED #define ADC_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
#define GET_ADC_SOURCE() (-1); #define GET_ADC_SOURCE() (-1);
#endif #endif
/* Not all the stm32 series have all the clock sources */
#if defined(RCC_ADC12CLKSOURCE_PLL) #if defined(RCC_ADC12CLKSOURCE_PLL)
#define ADC_SOURCE_PLL RCC_ADC12CLKSOURCE_PLL #define ADC_SOURCE_PLL RCC_ADC12CLKSOURCE_PLL
#elif defined(RCC_ADCCLKSOURCE_PLLADC) #elif defined(RCC_ADCCLKSOURCE_PLLADC)
@ -47,6 +46,14 @@
#define ADC_SOURCE_PLL (-1) #define ADC_SOURCE_PLL (-1)
#endif #endif
#if defined(RCC_ADC12CLKSOURCE_SYSCLK)
#define ADC_SOURCE_SYSCLK RCC_ADC12CLKSOURCE_SYSCLK
#elif defined(RCC_ADCCLKSOURCE_SYSCLK)
#define ADC_SOURCE_SYSCLK RCC_ADCCLKSOURCE_SYSCLK
#else
#define ADC_SOURCE_SYSCLK (-1)
#endif
ZTEST(stm32_common_devices_clocks, test_adc_clk_config) ZTEST(stm32_common_devices_clocks, test_adc_clk_config)
{ {
static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(adc1)); static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(adc1));
@ -87,13 +94,20 @@ ZTEST(stm32_common_devices_clocks, test_adc_clk_config)
dev_actual_clk_src = GET_ADC_SOURCE(); dev_actual_clk_src = GET_ADC_SOURCE();
switch (pclken[1].bus) { switch (pclken[1].bus) {
#if defined(STM32_SRC_SYSCLK)
case STM32_SRC_SYSCLK:
zassert_equal(dev_actual_clk_src, ADC_SOURCE_SYSCLK,
"Expected ADC1 src: SYSCLK (0x%lx). Actual ADC1 src: 0x%x",
ADC_SOURCE_SYSCLK, dev_actual_clk_src);
break;
#endif /* STM32_SRC_SYSCLK */
#if defined(STM32_SRC_PLL_P) #if defined(STM32_SRC_PLL_P)
case STM32_SRC_PLL_P: case STM32_SRC_PLL_P:
zassert_equal(dev_actual_clk_src, ADC_SOURCE_PLL, zassert_equal(dev_actual_clk_src, ADC_SOURCE_PLL,
"Expected ADC1 src: PLL (0x%lx). Actual ADC1 src: 0x%x", "Expected ADC1 src: PLL (0x%lx). Actual ADC1 src: 0x%x",
ADC_SOURCE_PLL, dev_actual_clk_src); ADC_SOURCE_PLL, dev_actual_clk_src);
break; break;
#endif #endif /* STM32_SRC_PLL_P */
default: default:
zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src);
} }