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drivers/spi: Always selecet HAS_DTS_SPI once SPI is enabled

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All drivers require DTS for their primary SPI settings.

Removing SPI_[0-9]_NAME config option added some more samples changes.
Usage of these options there was anyway not relevant.

Fixes #11064

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2018-11-15 09:02:14 -06:00 • committed by Anas Nashif
commit 1634cf2248
37 changed files with 70 additions and 151 deletions
Download patch file Download diff file Expand all files Collapse all files

48
drivers/spi/Kconfig
View file

@ -11,6 +11,7 @@
# #
menuconfig SPI menuconfig SPI
bool "SPI hardware bus support" bool "SPI hardware bus support"
select HAS_DTS_SPI
help help
Enable support for the SPI hardware bus. Enable support for the SPI hardware bus.
@ -46,11 +47,6 @@ config SPI_0
if SPI_0 if SPI_0
config SPI_0_NAME
string "SPI port 0 device name"
depends on !HAS_DTS_SPI
default "SPI_0"
config SPI_0_OP_MODES config SPI_0_OP_MODES
int "Port 0 supported operation modes (master/slave/both)" int "Port 0 supported operation modes (master/slave/both)"
default 1 default 1
@ -62,10 +58,6 @@ config SPI_0_OP_MODES
2 is SLAVE mode only 2 is SLAVE mode only
3 is both modes are available. 3 is both modes are available.
config SPI_0_IRQ_PRI
int "Port 0 interrupt priority"
depends on !HAS_DTS_SPI
endif # SPI_0 endif # SPI_0
config SPI_1 config SPI_1
@ -75,11 +67,6 @@ config SPI_1
if SPI_1 if SPI_1
config SPI_1_NAME
string "SPI port 1 device name"
depends on !HAS_DTS_SPI
default "SPI_1"
config SPI_1_OP_MODES config SPI_1_OP_MODES
int "Port 1 supported operation modes (master/slave/both)" int "Port 1 supported operation modes (master/slave/both)"
default 1 default 1
@ -91,10 +78,6 @@ config SPI_1_OP_MODES
2 is SLAVE mode only 2 is SLAVE mode only
3 is both modes are available. 3 is both modes are available.
config SPI_1_IRQ_PRI
int "Port 1 interrupt priority"
depends on !HAS_DTS_SPI
endif # SPI_1 endif # SPI_1
config SPI_2 config SPI_2
@ -104,11 +87,6 @@ config SPI_2
if SPI_2 if SPI_2
config SPI_2_NAME
string "SPI port 2 device name"
depends on !HAS_DTS_SPI
default "SPI_2"
config SPI_2_OP_MODES config SPI_2_OP_MODES
int "Port 2 supported operation modes (master/slave/both)" int "Port 2 supported operation modes (master/slave/both)"
default 1 default 1
@ -120,10 +98,6 @@ config SPI_2_OP_MODES
2 is SLAVE mode only 2 is SLAVE mode only
3 is both modes are available. 3 is both modes are available.
config SPI_2_IRQ_PRI
int "Port 2 interrupt priority"
depends on !HAS_DTS_SPI
endif # SPI_2 endif # SPI_2
config SPI_3 config SPI_3
@ -133,11 +107,6 @@ config SPI_3
if SPI_3 if SPI_3
config SPI_3_NAME
string "SPI port 3 device name"
depends on !HAS_DTS_SPI
default "SPI_3"
config SPI_3_OP_MODES config SPI_3_OP_MODES
int "Port 3 supported operation modes (master/slave/both)" int "Port 3 supported operation modes (master/slave/both)"
default 1 default 1
@ -149,10 +118,6 @@ config SPI_3_OP_MODES
2 is SLAVE mode only 2 is SLAVE mode only
3 is both modes are available. 3 is both modes are available.
config SPI_3_IRQ_PRI
int "Port 3 interrupt priority"
depends on !HAS_DTS_SPI
endif # SPI_3 endif # SPI_3
config SPI_4 config SPI_4
@ -162,11 +127,6 @@ config SPI_4
if SPI_4 if SPI_4
config SPI_4_NAME
string "SPI port 4 device name"
depends on !HAS_DTS_SPI
default "SPI_4"
config SPI_4_OP_MODES config SPI_4_OP_MODES
int "Port 4 supported operation modes (master/slave/both)" int "Port 4 supported operation modes (master/slave/both)"
default 1 default 1
@ -187,11 +147,6 @@ config SPI_5
if SPI_5 if SPI_5
config SPI_5_NAME
string "SPI port 5 device name"
depends on !HAS_DTS_SPI
default "SPI_5"
config SPI_5_OP_MODES config SPI_5_OP_MODES
int "Port 5 supported operation modes (master/slave/both)" int "Port 5 supported operation modes (master/slave/both)"
default 1 default 1
@ -208,7 +163,6 @@ endif # SPI_5
config SPI_INTEL config SPI_INTEL
bool "Intel SPI controller driver" bool "Intel SPI controller driver"
depends on CPU_MINUTEIA depends on CPU_MINUTEIA
select HAS_DTS_SPI
help help
Enable support for Intel's SPI controllers. Such controller Enable support for Intel's SPI controllers. Such controller
was formerly found on XScale chips. It can be found nowadays was formerly found on XScale chips. It can be found nowadays

1
drivers/spi/Kconfig.dw
View file

@ -8,7 +8,6 @@
menuconfig SPI_DW menuconfig SPI_DW
bool "Designware SPI controller driver" bool "Designware SPI controller driver"
select HAS_DTS_SPI
help help
Enable support for Designware's SPI controllers. Enable support for Designware's SPI controllers.

1
drivers/spi/Kconfig.mcux_dspi
View file

@ -9,6 +9,5 @@
menuconfig SPI_MCUX_DSPI menuconfig SPI_MCUX_DSPI
bool "MCUX SPI driver" bool "MCUX SPI driver"
depends on HAS_MCUX && CLOCK_CONTROL depends on HAS_MCUX && CLOCK_CONTROL
select HAS_DTS_SPI
help help
Enable support for mcux spi driver. Enable support for mcux spi driver.

1
drivers/spi/Kconfig.mcux_lpspi
View file

@ -8,6 +8,5 @@
menuconfig SPI_MCUX_LPSPI menuconfig SPI_MCUX_LPSPI
bool "MCUX SPI driver" bool "MCUX SPI driver"
depends on HAS_MCUX_LPSPI && CLOCK_CONTROL depends on HAS_MCUX_LPSPI && CLOCK_CONTROL
select HAS_DTS_SPI
help help
Enable support for mcux spi driver. Enable support for mcux spi driver.

1
drivers/spi/Kconfig.nrfx
View file

@ -6,7 +6,6 @@
menuconfig SPI_NRFX menuconfig SPI_NRFX
bool "nRF SPI nrfx drivers" bool "nRF SPI nrfx drivers"
depends on SOC_FAMILY_NRF depends on SOC_FAMILY_NRF
select HAS_DTS_SPI
help help
Enable support for nrfx SPI drivers for nRF MCU series. Enable support for nrfx SPI drivers for nRF MCU series.
Peripherals with the same instance ID cannot be used together, Peripherals with the same instance ID cannot be used together,

1
drivers/spi/Kconfig.sam
View file

@ -6,7 +6,6 @@
menuconfig SPI_SAM menuconfig SPI_SAM
bool "Atmel SAM series SPI driver" bool "Atmel SAM series SPI driver"
depends on SOC_FAMILY_SAM depends on SOC_FAMILY_SAM
select HAS_DTS_SPI
help help
Enable support for the SAM SPI driver. Enable support for the SAM SPI driver.

1
drivers/spi/Kconfig.sam0
View file

@ -6,6 +6,5 @@
menuconfig SPI_SAM0 menuconfig SPI_SAM0
bool "Atmel SAM0 series SERCOM SPI driver" bool "Atmel SAM0 series SERCOM SPI driver"
depends on SOC_FAMILY_SAM0 depends on SOC_FAMILY_SAM0
select HAS_DTS_SPI
help help
Enable support for the SAM0 SERCOM SPI driver. Enable support for the SAM0 SERCOM SPI driver.

1
drivers/spi/Kconfig.stm32
View file

@ -9,7 +9,6 @@
menuconfig SPI_STM32 menuconfig SPI_STM32
bool "STM32 MCU SPI controller driver" bool "STM32 MCU SPI controller driver"
depends on SPI && SOC_FAMILY_STM32 depends on SPI && SOC_FAMILY_STM32
select HAS_DTS_SPI
select USE_STM32_LL_SPI select USE_STM32_LL_SPI
help help
Enable SPI support on the STM32 family of processors. Enable SPI support on the STM32 family of processors.

8
drivers/spi/spi_dw.c
View file

@ -543,7 +543,7 @@ const struct spi_dw_config spi_dw_config_0 = {
.op_modes = CONFIG_SPI_0_OP_MODES .op_modes = CONFIG_SPI_0_OP_MODES
}; };
DEVICE_AND_API_INIT(spi_dw_port_0, CONFIG_SPI_0_NAME, spi_dw_init, DEVICE_AND_API_INIT(spi_dw_port_0, DT_SPI_0_NAME, spi_dw_init,
&spi_dw_data_port_0, &spi_dw_config_0, &spi_dw_data_port_0, &spi_dw_config_0,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&dw_spi_api); &dw_spi_api);
@ -591,7 +591,7 @@ static const struct spi_dw_config spi_dw_config_1 = {
.op_modes = CONFIG_SPI_1_OP_MODES .op_modes = CONFIG_SPI_1_OP_MODES
}; };
DEVICE_AND_API_INIT(spi_dw_port_1, CONFIG_SPI_1_NAME, spi_dw_init, DEVICE_AND_API_INIT(spi_dw_port_1, DT_SPI_1_NAME, spi_dw_init,
&spi_dw_data_port_1, &spi_dw_config_1, &spi_dw_data_port_1, &spi_dw_config_1,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&dw_spi_api); &dw_spi_api);
@ -639,7 +639,7 @@ static const struct spi_dw_config spi_dw_config_2 = {
.op_modes = CONFIG_SPI_2_OP_MODES .op_modes = CONFIG_SPI_2_OP_MODES
}; };
DEVICE_AND_API_INIT(spi_dw_port_2, CONFIG_SPI_2_NAME, spi_dw_init, DEVICE_AND_API_INIT(spi_dw_port_2, DT_SPI_2_NAME, spi_dw_init,
&spi_dw_data_port_2, &spi_dw_config_2, &spi_dw_data_port_2, &spi_dw_config_2,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&dw_spi_api); &dw_spi_api);
@ -687,7 +687,7 @@ static const struct spi_dw_config spi_dw_config_3 = {
.op_modes = CONFIG_SPI_3_OP_MODES .op_modes = CONFIG_SPI_3_OP_MODES
}; };
DEVICE_AND_API_INIT(spi_dw_port_3, CONFIG_SPI_3_NAME, spi_dw_init, DEVICE_AND_API_INIT(spi_dw_port_3, DT_SPI_3_NAME, spi_dw_init,
&spi_dw_data_port_3, &spi_dw_config_3, &spi_dw_data_port_3, &spi_dw_config_3,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&dw_spi_api); &dw_spi_api);

4
drivers/spi/spi_intel.c
View file

@ -432,7 +432,7 @@ const struct spi_intel_config spi_intel_config_0 = {
.config_func = spi_config_0_irq .config_func = spi_config_0_irq
}; };
DEVICE_DEFINE(spi_intel_port_0, CONFIG_SPI_0_NAME, spi_intel_init, DEVICE_DEFINE(spi_intel_port_0, DT_SPI_0_NAME, spi_intel_init,
spi_intel_device_ctrl, &spi_intel_data_port_0, spi_intel_device_ctrl, &spi_intel_data_port_0,
&spi_intel_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_intel_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&intel_spi_api); &intel_spi_api);
@ -468,7 +468,7 @@ const struct spi_intel_config spi_intel_config_1 = {
.config_func = spi_config_1_irq .config_func = spi_config_1_irq
}; };
DEVICE_DEFINE(spi_intel_port_1, CONFIG_SPI_1_NAME, spi_intel_init, DEVICE_DEFINE(spi_intel_port_1, DT_SPI_1_NAME, spi_intel_init,
spi_intel_device_ctrl, &spi_intel_data_port_1, spi_intel_device_ctrl, &spi_intel_data_port_1,
&spi_intel_config_1, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_intel_config_1, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&intel_spi_api); &intel_spi_api);

6
drivers/spi/spi_ll_stm32.c
View file

@ -504,7 +504,7 @@ static struct spi_stm32_data spi_stm32_dev_data_1 = {
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_1, ctx), SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_1, ctx),
}; };
DEVICE_AND_API_INIT(spi_stm32_1, CONFIG_SPI_1_NAME, &spi_stm32_init, DEVICE_AND_API_INIT(spi_stm32_1, DT_SPI_1_NAME, &spi_stm32_init,
&spi_stm32_dev_data_1, &spi_stm32_cfg_1, &spi_stm32_dev_data_1, &spi_stm32_cfg_1,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&api_funcs); &api_funcs);
@ -542,7 +542,7 @@ static struct spi_stm32_data spi_stm32_dev_data_2 = {
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_2, ctx), SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_2, ctx),
}; };
DEVICE_AND_API_INIT(spi_stm32_2, CONFIG_SPI_2_NAME, &spi_stm32_init, DEVICE_AND_API_INIT(spi_stm32_2, DT_SPI_2_NAME, &spi_stm32_init,
&spi_stm32_dev_data_2, &spi_stm32_cfg_2, &spi_stm32_dev_data_2, &spi_stm32_cfg_2,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&api_funcs); &api_funcs);
@ -580,7 +580,7 @@ static struct spi_stm32_data spi_stm32_dev_data_3 = {
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_3, ctx), SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_3, ctx),
}; };
DEVICE_AND_API_INIT(spi_stm32_3, CONFIG_SPI_3_NAME, &spi_stm32_init, DEVICE_AND_API_INIT(spi_stm32_3, DT_SPI_3_NAME, &spi_stm32_init,
&spi_stm32_dev_data_3, &spi_stm32_cfg_3, &spi_stm32_dev_data_3, &spi_stm32_cfg_3,
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&api_funcs); &api_funcs);

6
drivers/spi/spi_mcux_dspi.c
View file

@ -277,7 +277,7 @@ static struct spi_mcux_data spi_mcux_data_0 = {
SPI_CONTEXT_INIT_SYNC(spi_mcux_data_0, ctx), SPI_CONTEXT_INIT_SYNC(spi_mcux_data_0, ctx),
}; };
DEVICE_AND_API_INIT(spi_mcux_0, CONFIG_SPI_0_NAME, &spi_mcux_init, DEVICE_AND_API_INIT(spi_mcux_0, DT_SPI_0_NAME, &spi_mcux_init,
&spi_mcux_data_0, &spi_mcux_config_0, &spi_mcux_data_0, &spi_mcux_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&spi_mcux_driver_api); &spi_mcux_driver_api);
@ -306,7 +306,7 @@ static struct spi_mcux_data spi_mcux_data_1 = {
SPI_CONTEXT_INIT_SYNC(spi_mcux_data_1, ctx), SPI_CONTEXT_INIT_SYNC(spi_mcux_data_1, ctx),
}; };
DEVICE_AND_API_INIT(spi_mcux_1, CONFIG_SPI_1_NAME, &spi_mcux_init, DEVICE_AND_API_INIT(spi_mcux_1, DT_SPI_1_NAME, &spi_mcux_init,
&spi_mcux_data_1, &spi_mcux_config_1, &spi_mcux_data_1, &spi_mcux_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&spi_mcux_driver_api); &spi_mcux_driver_api);
@ -335,7 +335,7 @@ static struct spi_mcux_data spi_mcux_data_2 = {
SPI_CONTEXT_INIT_SYNC(spi_mcux_data_2, ctx), SPI_CONTEXT_INIT_SYNC(spi_mcux_data_2, ctx),
}; };
DEVICE_AND_API_INIT(spi_mcux_2, CONFIG_SPI_2_NAME, &spi_mcux_init, DEVICE_AND_API_INIT(spi_mcux_2, DT_SPI_2_NAME, &spi_mcux_init,
&spi_mcux_data_2, &spi_mcux_config_2, &spi_mcux_data_2, &spi_mcux_config_2,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&spi_mcux_driver_api); &spi_mcux_driver_api);

2
drivers/spi/spi_nrfx_spim.c
View file

@ -335,7 +335,7 @@ static int init_spim(struct device *dev, const nrfx_spim_config_t *config)
.spim = NRFX_SPIM_INSTANCE(idx), \ .spim = NRFX_SPIM_INSTANCE(idx), \
.max_chunk_len = (1 << SPIM##idx##_EASYDMA_MAXCNT_SIZE) - 1, \ .max_chunk_len = (1 << SPIM##idx##_EASYDMA_MAXCNT_SIZE) - 1, \
}; \ }; \
DEVICE_AND_API_INIT(spi_##idx, CONFIG_SPI_##idx##_NAME, \ DEVICE_AND_API_INIT(spi_##idx, DT_SPI_##idx##_NAME, \
spi_##idx##_init, \ spi_##idx##_init, \
&spi_##idx##_data, \ &spi_##idx##_data, \
&spi_##idx##_config, \ &spi_##idx##_config, \

2
drivers/spi/spi_nrfx_spis.c
View file

@ -275,7 +275,7 @@ static int init_spis(struct device *dev, const nrfx_spis_config_t *config)
.spis = NRFX_SPIS_INSTANCE(idx), \ .spis = NRFX_SPIS_INSTANCE(idx), \
.max_buf_len = (1 << SPIS##idx##_EASYDMA_MAXCNT_SIZE) - 1, \ .max_buf_len = (1 << SPIS##idx##_EASYDMA_MAXCNT_SIZE) - 1, \
}; \ }; \
DEVICE_AND_API_INIT(spi_##idx, CONFIG_SPI_##idx##_NAME, \ DEVICE_AND_API_INIT(spi_##idx, DT_SPI_##idx##_NAME, \
spi_##idx##_init, \ spi_##idx##_init, \
&spi_##idx##_data, \ &spi_##idx##_data, \
&spi_##idx##_config, \ &spi_##idx##_config, \

1
samples/drivers/led_lpd8806/boards/96b_carbon.conf
View file

@ -1,4 +1,3 @@
CONFIG_SPI_STM32=y CONFIG_SPI_STM32=y
CONFIG_SPI_STM32_INTERRUPT=y CONFIG_SPI_STM32_INTERRUPT=y
CONFIG_SPI_2=y CONFIG_SPI_2=y
CONFIG_SPI_2_NAME="lpd8806_spi"

13
samples/drivers/led_lpd8806/src/main.c
View file

@ -22,7 +22,6 @@ LOG_MODULE_REGISTER(main);
*/ */
#define STRIP_NUM_LEDS 32 #define STRIP_NUM_LEDS 32
#define SPI_DEV_NAME "lpd8806_spi"
#define STRIP_DEV_NAME CONFIG_LPD880X_STRIP_NAME #define STRIP_DEV_NAME CONFIG_LPD880X_STRIP_NAME
#define DELAY_TIME K_MSEC(40) #define DELAY_TIME K_MSEC(40)
@ -53,19 +52,9 @@ const struct led_rgb *color_at(size_t time, size_t i)
void main(void) void main(void)
{ {
struct device *spi, *strip; struct device *strip;
size_t i, time; size_t i, time;
/* Double-check the configuration. */
spi = device_get_binding(SPI_DEV_NAME);
if (spi) {
LOG_INF("Found SPI device %s", SPI_DEV_NAME);
} else {
LOG_ERR("SPI device not found; you must choose a SPI "
"device and configure its name to %s",
SPI_DEV_NAME);
return;
}
strip = device_get_binding(STRIP_DEV_NAME); strip = device_get_binding(STRIP_DEV_NAME);
if (strip) { if (strip) {
LOG_INF("Found LED strip device %s", STRIP_DEV_NAME); LOG_INF("Found LED strip device %s", STRIP_DEV_NAME);

7
samples/drivers/led_ws2812/boards/96b_carbon.conf
View file

@ -1,10 +1,9 @@
CONFIG_POLL=y CONFIG_POLL=y
CONFIG_SPI=y CONFIG_SPI=y
CONFIG_WS2812_STRIP=y
CONFIG_WS2812_STRIP_SPI_DEV_NAME="ws2812_spi"
CONFIG_SPI_STM32=y CONFIG_SPI_STM32=y
CONFIG_SPI_STM32_INTERRUPT=y CONFIG_SPI_STM32_INTERRUPT=y
CONFIG_SPI_2=y CONFIG_SPI_2=y
CONFIG_SPI_2_NAME="ws2812_spi"
CONFIG_WS2812_STRIP=y
CONFIG_WS2812_STRIP_SPI_DEV_NAME="SPI_2"

15
samples/drivers/led_ws2812/src/main.c
View file

@ -29,7 +29,6 @@ LOG_MODULE_REGISTER(main);
#define STRIP_DEV_NAME CONFIG_WS2812B_SW_NAME #define STRIP_DEV_NAME CONFIG_WS2812B_SW_NAME
#endif #endif
#define SPI_DEV_NAME "ws2812_spi"
#define DELAY_TIME K_MSEC(40) #define DELAY_TIME K_MSEC(40)
static const struct led_rgb colors[] = { static const struct led_rgb colors[] = {
@ -61,20 +60,6 @@ void main(void)
{ {
struct device *strip; struct device *strip;
size_t i, time; size_t i, time;
#if defined(CONFIG_SPI)
struct device *spi;
/* Double-check the configuration. */
spi = device_get_binding(SPI_DEV_NAME);
if (spi) {
LOG_INF("Found SPI device %s", SPI_DEV_NAME);
} else {
LOG_ERR("SPI device not found; you must choose a SPI "
"device and configure its name to %s",
SPI_DEV_NAME);
return;
}
#endif
strip = device_get_binding(STRIP_DEV_NAME); strip = device_get_binding(STRIP_DEV_NAME);
if (strip) { if (strip) {

2
samples/drivers/spi_fujitsu_fram/src/main.c
View file

@ -143,7 +143,7 @@ void main(void)
printk("fujitsu FRAM example application\n"); printk("fujitsu FRAM example application\n");
spi = device_get_binding(CONFIG_SPI_1_NAME); spi = device_get_binding(DT_SPI_1_NAME);
if (!spi) { if (!spi) {
printk("Could not find SPI driver\n"); printk("Could not find SPI driver\n");
return; return;

4
soc/arc/quark_se_c1000_ss/dts_fixup.h
View file

@ -75,7 +75,7 @@
#define DT_ADC_0_BASE_ADDRESS DT_SNPS_DW_ADC_80015000_BASE_ADDRESS #define DT_ADC_0_BASE_ADDRESS DT_SNPS_DW_ADC_80015000_BASE_ADDRESS
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_80010000_LABEL #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_80010000_LABEL
#define DT_SPI_0_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT #define DT_SPI_0_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT
#define DT_SPI_0_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY #define DT_SPI_0_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY
#define DT_SPI_0_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL #define DT_SPI_0_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL
@ -84,7 +84,7 @@
#define DT_SPI_0_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY #define DT_SPI_0_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS
#define CONFIG_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_80010100_LABEL #define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_80010100_LABEL
#define DT_SPI_1_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT #define DT_SPI_1_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT
#define DT_SPI_1_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY #define DT_SPI_1_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY
#define DT_SPI_1_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL #define DT_SPI_1_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL

4
soc/arc/snps_emsk/dts_fixup.h
View file

@ -84,12 +84,12 @@
*/ */
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0 #define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS
#define CONFIG_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL #define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL
#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0 #define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY

4
soc/arm/atmel_sam/same70/dts_fixup.h
View file

@ -56,13 +56,13 @@
#define DT_I2C_2_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40060000_PERIPHERAL_ID #define DT_I2C_2_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40060000_PERIPHERAL_ID
#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL #define DT_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL
#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0 #define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY
#define DT_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40008000_PERIPHERAL_ID #define DT_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40008000_PERIPHERAL_ID
#define DT_SPI_1_BASE_ADDRESS DT_ATMEL_SAM_SPI_40058000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ATMEL_SAM_SPI_40058000_BASE_ADDRESS
#define CONFIG_SPI_1_NAME DT_ATMEL_SAM_SPI_40058000_LABEL #define DT_SPI_1_NAME DT_ATMEL_SAM_SPI_40058000_LABEL
#define DT_SPI_1_IRQ DT_ATMEL_SAM_SPI_40058000_IRQ_0 #define DT_SPI_1_IRQ DT_ATMEL_SAM_SPI_40058000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY
#define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID #define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID

4
soc/arm/nordic_nrf/nrf51/dts_fixup.h
View file

@ -58,7 +58,7 @@
#define DT_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS #define DT_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS
#define DT_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_NORDIC_NRF_SPI_40003000_LABEL #define DT_SPI_0_NAME DT_NORDIC_NRF_SPI_40003000_LABEL
#define CONFIG_SPI_0_IRQ_PRI DT_NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0 #define DT_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0
#define DT_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN #define DT_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN
@ -67,7 +67,7 @@
#define DT_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN #define DT_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN
#define DT_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS
#define CONFIG_SPI_1_NAME DT_NORDIC_NRF_SPI_40004000_LABEL #define DT_SPI_1_NAME DT_NORDIC_NRF_SPI_40004000_LABEL
#define CONFIG_SPI_1_IRQ_PRI DT_NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0 #define DT_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0
#define DT_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN #define DT_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN

8
soc/arm/nordic_nrf/nrf52/dts_fixup.h
View file

@ -91,7 +91,7 @@
#define DT_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS #define DT_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS
#define DT_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_NORDIC_NRF_SPI_40003000_LABEL #define DT_SPI_0_NAME DT_NORDIC_NRF_SPI_40003000_LABEL
#define CONFIG_SPI_0_IRQ_PRI DT_NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0 #define DT_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0
#define DT_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN #define DT_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN
@ -100,7 +100,7 @@
#define DT_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN #define DT_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN
#define DT_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS
#define CONFIG_SPI_1_NAME DT_NORDIC_NRF_SPI_40004000_LABEL #define DT_SPI_1_NAME DT_NORDIC_NRF_SPI_40004000_LABEL
#define CONFIG_SPI_1_IRQ_PRI DT_NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0 #define DT_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0
#define DT_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN #define DT_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN
@ -109,7 +109,7 @@
#define DT_SPI_1_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40004000_CSN_PIN #define DT_SPI_1_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40004000_CSN_PIN
#define DT_SPI_2_BASE_ADDRESS DT_NORDIC_NRF_SPI_40023000_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_NORDIC_NRF_SPI_40023000_BASE_ADDRESS
#define CONFIG_SPI_2_NAME DT_NORDIC_NRF_SPI_40023000_LABEL #define DT_SPI_2_NAME DT_NORDIC_NRF_SPI_40023000_LABEL
#define CONFIG_SPI_2_IRQ_PRI DT_NORDIC_NRF_SPI_40023000_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_NORDIC_NRF_SPI_40023000_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ DT_NORDIC_NRF_SPI_40023000_IRQ_0 #define DT_SPI_2_IRQ DT_NORDIC_NRF_SPI_40023000_IRQ_0
#define DT_SPI_2_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40023000_SCK_PIN #define DT_SPI_2_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40023000_SCK_PIN
@ -118,7 +118,7 @@
#define DT_SPI_2_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40023000_CSN_PIN #define DT_SPI_2_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40023000_CSN_PIN
#define DT_SPI_3_BASE_ADDRESS DT_NORDIC_NRF_SPI_4002B000_BASE_ADDRESS #define DT_SPI_3_BASE_ADDRESS DT_NORDIC_NRF_SPI_4002B000_BASE_ADDRESS
#define CONFIG_SPI_3_NAME DT_NORDIC_NRF_SPI_4002B000_LABEL #define DT_SPI_3_NAME DT_NORDIC_NRF_SPI_4002B000_LABEL
#define CONFIG_SPI_3_IRQ_PRI DT_NORDIC_NRF_SPI_4002B000_IRQ_0_PRIORITY #define CONFIG_SPI_3_IRQ_PRI DT_NORDIC_NRF_SPI_4002B000_IRQ_0_PRIORITY
#define DT_SPI_3_IRQ DT_NORDIC_NRF_SPI_4002B000_IRQ_0 #define DT_SPI_3_IRQ DT_NORDIC_NRF_SPI_4002B000_IRQ_0
#define DT_SPI_3_NRF_SCK_PIN DT_NORDIC_NRF_SPI_4002B000_SCK_PIN #define DT_SPI_3_NRF_SCK_PIN DT_NORDIC_NRF_SPI_4002B000_SCK_PIN

6
soc/arm/nxp_kinetis/k6x/dts_fixup.h
View file

@ -95,21 +95,21 @@
#define DT_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER #define DT_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER
#define DT_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME #define DT_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME
#define CONFIG_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL #define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 #define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER #define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME #define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
#define CONFIG_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL #define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 #define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER #define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME #define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
#define CONFIG_SPI_2_NAME DT_NXP_KINETIS_DSPI_400AC000_LABEL #define DT_SPI_2_NAME DT_NXP_KINETIS_DSPI_400AC000_LABEL
#define DT_SPI_2_BASE_ADDRESS DT_NXP_KINETIS_DSPI_400AC000_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_NXP_KINETIS_DSPI_400AC000_BASE_ADDRESS
#define DT_SPI_2_IRQ DT_NXP_KINETIS_DSPI_400AC000_IRQ_0 #define DT_SPI_2_IRQ DT_NXP_KINETIS_DSPI_400AC000_IRQ_0
#define CONFIG_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY

8
soc/arm/nxp_kinetis/kwx/dts_fixup.h
View file

@ -81,14 +81,14 @@
#define DT_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER #define DT_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER
#define DT_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME #define DT_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME
#define CONFIG_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL #define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 #define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER #define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME #define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
#define CONFIG_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL #define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 #define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
@ -131,14 +131,14 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS #define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL #define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL
#define CONFIG_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL #define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 #define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER #define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME #define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
#define CONFIG_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL #define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 #define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY

4
soc/arm/st_stm32/stm32f0/dts_fixup.h
View file

@ -90,12 +90,12 @@
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL #define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 #define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL #define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 #define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS #define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS

6
soc/arm/st_stm32/stm32f1/dts_fixup.h
View file

@ -119,17 +119,17 @@
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL #define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 #define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL #define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 #define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS #define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL #define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 #define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0
#define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS #define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS

8
soc/arm/st_stm32/stm32f3/dts_fixup.h
View file

@ -112,22 +112,22 @@
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL #define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 #define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL #define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 #define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS #define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL #define DT_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0 #define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0
#define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS #define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS
#define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY #define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY
#define CONFIG_SPI_4_NAME DT_ST_STM32_SPI_FIFO_40013C00_LABEL #define DT_SPI_4_NAME DT_ST_STM32_SPI_FIFO_40013C00_LABEL
#define DT_SPI_4_IRQ DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0 #define DT_SPI_4_IRQ DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS #define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS

10
soc/arm/st_stm32/stm32f4/dts_fixup.h
View file

@ -165,27 +165,27 @@
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL #define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 #define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL #define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 #define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS #define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL #define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 #define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0
#define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS #define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS
#define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY #define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY
#define CONFIG_SPI_4_NAME DT_ST_STM32_SPI_40013400_LABEL #define DT_SPI_4_NAME DT_ST_STM32_SPI_40013400_LABEL
#define DT_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0 #define DT_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0
#define DT_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS #define DT_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS
#define DT_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY #define DT_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY
#define CONFIG_SPI_5_NAME DT_ST_STM32_SPI_40015000_LABEL #define DT_SPI_5_NAME DT_ST_STM32_SPI_40015000_LABEL
#define DT_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0 #define DT_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0
#define DT_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS #define DT_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS

10
soc/arm/st_stm32/stm32f7/dts_fixup.h
View file

@ -197,27 +197,27 @@
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL #define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 #define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL #define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 #define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS #define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL #define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 #define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0
#define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS #define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS
#define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY #define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY
#define CONFIG_SPI_4_NAME DT_ST_STM32_SPI_40013400_LABEL #define DT_SPI_4_NAME DT_ST_STM32_SPI_40013400_LABEL
#define DT_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0 #define DT_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0
#define DT_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS #define DT_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS
#define DT_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY #define DT_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY
#define CONFIG_SPI_5_NAME DT_ST_STM32_SPI_40015000_LABEL #define DT_SPI_5_NAME DT_ST_STM32_SPI_40015000_LABEL
#define DT_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0 #define DT_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0
#define DT_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS #define DT_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS

4
soc/arm/st_stm32/stm32l0/dts_fixup.h
View file

@ -108,12 +108,12 @@
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL #define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 #define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL #define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 #define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
#define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS #define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS

6
soc/arm/st_stm32/stm32l4/dts_fixup.h
View file

@ -179,17 +179,17 @@
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL #define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 #define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL #define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 #define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS #define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL #define DT_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0 #define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32L4_FLASH_CONTROLLER_40022000_BASE_ADDRESS #define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32L4_FLASH_CONTROLLER_40022000_BASE_ADDRESS

2
soc/x86/intel_quark/quark_d2000/dts_fixup.h
View file

@ -35,7 +35,7 @@
#define DT_ADC_0_IRQ_FLAGS DT_INTEL_QUARK_D2000_ADC_B0004000_IRQ_0_SENSE #define DT_ADC_0_IRQ_FLAGS DT_INTEL_QUARK_D2000_ADC_B0004000_IRQ_0_SENSE
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 #define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI 0 #define CONFIG_SPI_0_IRQ_PRI 0

6
soc/x86/intel_quark/quark_se/dts_fixup.h
View file

@ -48,17 +48,17 @@
#define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE #define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 #define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS
#define CONFIG_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL #define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL
#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0 #define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY
#define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS #define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS
#define CONFIG_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL #define DT_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL
#define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0 #define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0
#define CONFIG_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY #define CONFIG_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY

4
soc/x86/intel_quark/quark_x1000/dts_fixup.h
View file

@ -34,10 +34,10 @@
#define DT_SPI_0_IRQ DT_INTEL_INTEL_SPI_90009000_IRQ_0 #define DT_SPI_0_IRQ DT_INTEL_INTEL_SPI_90009000_IRQ_0
#define DT_SPI_0_IRQ_FLAGS DT_INTEL_INTEL_SPI_90009000_IRQ_0_SENSE #define DT_SPI_0_IRQ_FLAGS DT_INTEL_INTEL_SPI_90009000_IRQ_0_SENSE
#define CONFIG_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY #define CONFIG_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY
#define CONFIG_SPI_0_NAME DT_INTEL_INTEL_SPI_90009000_LABEL #define DT_SPI_0_NAME DT_INTEL_INTEL_SPI_90009000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_INTEL_INTEL_SPI_90008000_BASE_ADDRESS #define DT_SPI_1_BASE_ADDRESS DT_INTEL_INTEL_SPI_90008000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_INTEL_INTEL_SPI_90008000_IRQ_0 #define DT_SPI_1_IRQ DT_INTEL_INTEL_SPI_90008000_IRQ_0
#define DT_SPI_1_IRQ_FLAGS DT_INTEL_INTEL_SPI_90008000_IRQ_0_SENSE #define DT_SPI_1_IRQ_FLAGS DT_INTEL_INTEL_SPI_90008000_IRQ_0_SENSE
#define CONFIG_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY #define CONFIG_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME DT_INTEL_INTEL_SPI_90008000_LABEL #define DT_SPI_1_NAME DT_INTEL_INTEL_SPI_90008000_LABEL

2
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -48,7 +48,7 @@
#define DT_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY #define DT_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS #define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_E000_LABEL #define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_E000_LABEL
#define DT_SPI_0_IRQ ((DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0 << 16) | \ #define DT_SPI_0_IRQ ((DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0 << 16) | \
(DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ (DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \