Merge "Merge remote-tracking branch 'origin/core'"

include/arch/cpu.h

@@ -19,6 +19,8 @@
 #include <arch/nios2/arch.h>
 #elif defined(CONFIG_RISCV32)
 #include <arch/riscv32/arch.h>
+#elif defined(CONFIG_XTENSA)
+#include <arch/xtensa/arch.h>
 #else
 #error "Unknown Architecture"
 #endif

include/arch/xtensa/addr_types.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef XTENSA_ADDR_TYPES_H
+#define XTENSA_ADDR_TYPES_H
+
+#ifndef _ASMLANGUAGE
+typedef unsigned int paddr_t;
+typedef unsigned int vaddr_t;
+#endif
+
+#endif /* XTENSA_ADDR_TYPES_H */
+

include/arch/xtensa/arch.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Xtensa specific kernel interface header
+ * This header contains the Xtensa specific kernel interface.  It is included
+ * by the generic kernel interface header (include/arch/cpu.h)
+ */
+
+#ifndef _ARCH_IFACE_H
+#define _ARCH_IFACE_H
+
+#include <irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
+#include "sys_io.h" /* Include from the very same folder of this file */
+#include <stdint.h>
+#include <sw_isr_table.h>
+#include <arch/xtensa/xtensa_irq.h>
+#include <xtensa/config/core.h>
+
+/*
+ * XCC does not define the following macros with the expected names, but the
+ * file machine/endian.h from XT_LIB defines similar ones. Thus we include it
+ * and define the missing macros ourselves.
+ */
+#define __BYTE_ORDER__ XCHAL_MEMORY_ORDER
+#define __ORDER_BIG_ENDIAN__ XTHAL_BIGENDIAN
+#define __ORDER_LITTLE_ENDIAN__ XTHAL_LITTLEENDIAN
+
+#define STACK_ALIGN 16
+#define OCTET_TO_SIZEOFUNIT(X) (X)
+#define SIZEOFUNIT_TO_OCTET(X) (X)
+
+#define _NANO_ERR_HW_EXCEPTION (0)      /* MPU/Bus/Usage fault */
+#define _NANO_ERR_INVALID_TASK_EXIT (1) /* Invalid task exit */
+#define _NANO_ERR_STACK_CHK_FAIL (2)    /* Stack corruption detected */
+#define _NANO_ERR_ALLOCATION_FAIL (3)   /* Kernel Allocation Failure */
+#define _NANO_ERR_RESERVED_IRQ (4)	/* Reserved interrupt */
+
+/* Xtensa GPRs are often designated by two different names */
+#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
+
+#include <arch/xtensa/exc.h>
+
+/**
+ *
+ * @brief find most significant bit set in a 32-bit word
+ *
+ * This routine finds the first bit set starting from the most significant bit
+ * in the argument passed in and returns the index of that bit.  Bits are
+ * numbered starting at 1 from the least significant bit.  A return value of
+ * zero indicates that the value passed is zero.
+ *
+ * @return most significant bit set, 0 if @a op is 0
+ */
+
+static ALWAYS_INLINE unsigned int find_msb_set(uint32_t op)
+{
+	if (!op)
+		return 0;
+	return 32 - __builtin_clz(op);
+}
+
+/**
+ *
+ * @brief find least significant bit set in a 32-bit word
+ *
+ * This routine finds the first bit set starting from the least significant bit
+ * in the argument passed in and returns the index of that bit.  Bits are
+ * numbered starting at 1 from the least significant bit.  A return value of
+ * zero indicates that the value passed is zero.
+ *
+ * @return least significant bit set, 0 if @a op is 0
+ */
+
+static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op)
+{
+	return __builtin_ffs(op);
+}
+
+/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
+extern void _irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags);
+
+
+/**
+ * Configure a static interrupt.
+ *
+ * All arguments must be computable by the compiler at build time; if this
+ * can't be done use irq_connect_dynamic() instead.
+ *
+ * Internally this function does a few things:
+ *
+ * 1. The enum statement has no effect but forces the compiler to only
+ * accept constant values for the irq_p parameter, very important as the
+ * numerical IRQ line is used to create a named section.
+ *
+ * 2. An instance of _isr_table_entry is created containing the ISR and its
+ * parameter. If you look at how _sw_isr_table is created, each entry in the
+ * array is in its own section named by the IRQ line number. What we are doing
+ * here is to override one of the default entries (which points to the
+ * spurious IRQ handler) with what was supplied here.
+ *
+ * 3. The priority level for the interrupt is configured by a call to
+ * _irq_priority_set()
+ *
+ * @param irq_p IRQ line number
+ * @param priority_p Interrupt priority
+ * @param isr_p Interrupt service routine
+ * @param isr_param_p ISR parameter
+ * @param flags_p IRQ options
+ *
+ * @return The vector assigned to this interrupt
+ */
+#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
+({ \
+	enum { IRQ = irq_p }; \
+	static struct _isr_table_entry \
+		_CONCAT(_isr_irq, irq_p) \
+		__attribute__ ((used)) \
+		__attribute__ ((section(\
+			STRINGIFY(_CONCAT(.gnu.linkonce.d.isr_irq, irq_p)))\
+		)) = {isr_param_p, isr_p}; \
+	_irq_priority_set(irq_p, priority_p, flags_p); \
+	irq_p; \
+})
+
+
+FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
+					 const NANO_ESF *esf);
+
+#endif /* !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ARCH_IFACE_H */

include/arch/xtensa/exc.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Xtensa public exception handling
+ *
+ * Xtensa-specific nanokernel exception handling interface. Included by
+ * arch/xtensa/arch.h.
+ */
+
+#ifndef _ARCH_XTENSA_EXC_H_
+#define _ARCH_XTENSA_EXC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef _ASMLANGUAGE
+#else
+/**
+ * @brief Nanokernel Exception Stack Frame
+ *
+ * A pointer to an "exception stack frame" (ESF) is passed as an argument
+ * to exception handlers registered via nanoCpuExcConnect().
+ */
+struct __esf {
+	/* XXX - not finished yet */
+	sys_define_gpr_with_alias(a1, sp);
+	uint32_t pc;
+};
+
+typedef struct __esf NANO_ESF;
+extern const NANO_ESF _default_esf;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARCH_XTENSA_EXC_H_ */

include/arch/xtensa/offsets.h

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef OFFSETS_H
+#define OFFSETS_H
+
+
+
+#endif /* OFFSETS_H */

include/arch/xtensa/sys_io.h

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef XTENSA_SYS_IO_H
+#define XTENSA_SYS_IO_H
+
+#if !defined(_ASMLANGUAGE)
+
+#include <sys_io.h>
+
+/* Memory mapped registers I/O functions */
+
+static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
+{
+	return *(volatile uint32_t *)addr;
+}
+
+
+static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
+{
+	*(volatile uint32_t *)addr = data;
+}
+
+
+/* Memory bit manipulation functions */
+
+static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	uint32_t temp = *(volatile uint32_t *)addr;
+
+	*(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	uint32_t temp = *(volatile uint32_t *)addr;
+
+	*(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit)
+{
+	int temp = *(volatile int *)addr;
+
+	return (int)(temp & (1 << bit));
+}
+
+static ALWAYS_INLINE int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	int retval = (*(volatile int *)addr) & (1 << bit);
+	*(volatile int *)addr = (*(volatile int *)addr) | (1 << bit);
+	return retval;
+}
+
+static ALWAYS_INLINE
+	int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	int retval = (*(volatile int *)addr) & (1 << bit);
+	*(volatile int *)addr = (*(volatile int *)addr) & ~(1 << bit);
+	return retval;
+}
+
+static ALWAYS_INLINE
+	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	/* Doing memory offsets in terms of 32-bit values to prevent
+	 * alignment issues
+	 */
+	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
+}
+
+static ALWAYS_INLINE
+	void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
+}
+
+static ALWAYS_INLINE
+	int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
+{
+	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
+}
+
+
+static ALWAYS_INLINE
+	int sys_bitfield_test_and_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	int ret;
+
+	ret = sys_bitfield_test_bit(addr, bit);
+	sys_bitfield_set_bit(addr, bit);
+
+	return ret;
+}
+
+static ALWAYS_INLINE
+	int sys_bitfield_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	int ret;
+
+	ret = sys_bitfield_test_bit(addr, bit);
+	sys_bitfield_clear_bit(addr, bit);
+
+	return ret;
+}
+
+
+#endif /* !_ASMLANGUAGE */
+
+
+#endif /* XTENSA_SYS_IO_H */

include/arch/xtensa/xtensa_irq.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef XTENSA_IRQ_H
+#define XTENSA_IRQ_H
+
+#include <xtensa_api.h>
+#include <xtensa/xtruntime.h>
+
+/**
+ *
+ * @brief Enable an interrupt line
+ *
+ * Clear possible pending interrupts on the line, and enable the interrupt
+ * line. After this call, the CPU will receive interrupts for the specified
+ * IRQ.
+ *
+ * @return N/A
+ */
+static ALWAYS_INLINE void _arch_irq_enable(uint32_t irq)
+{
+	_xt_ints_on(1 << irq);
+}
+
+/**
+ *
+ * @brief Disable an interrupt line
+ *
+ * Disable an interrupt line. After this call, the CPU will stop receiving
+ * interrupts for the specified IRQ.
+ *
+ * @return N/A
+ */
+static ALWAYS_INLINE void _arch_irq_disable(uint32_t irq)
+{
+	_xt_ints_off(1 << irq);
+}
+
+static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
+{
+	unsigned int key = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
+	return key;
+}
+
+static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
+{
+	XTOS_RESTORE_INTLEVEL(key);
+}
+
+#include <irq.h>
+
+#endif /* XTENSA_IRQ_H */