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arch: arm: use CMSIS defines for MPU_RASR register bit setting

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This commit removes the macro definitions for MPU_RASR register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2018-06-18 12:40:43 +02:00 • committed by Maureen Helm
commit 1547abb57d
3 changed files with 15 additions and 33 deletions
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12
arch/arm/core/cortex_m/mpu/arm_mpu.c
View file

@ -112,7 +112,7 @@ static void _region_init(u32_t index, u32_t region_addr,
/* Configure the region */
ARM_MPU_DEV->rbar = (region_addr & MPU_RBAR_ADDR_Msk)
| MPU_RBAR_VALID_Msk | index;
ARM_MPU_DEV->rasr = region_attr | REGION_ENABLE;
ARM_MPU_DEV->rasr = region_attr | MPU_RASR_ENABLE_Msk;
SYS_LOG_DBG("[%d] 0x%08x 0x%08x", index, region_addr, region_attr);
}
@ -184,7 +184,7 @@ static inline int _is_enabled_region(u32_t r_index)
{
ARM_MPU_DEV->rnr = r_index;
return ARM_MPU_DEV->rasr & REGION_ENABLE_MASK;
return ARM_MPU_DEV->rasr & MPU_RASR_ENABLE_Msk;
}
/**
@ -201,8 +201,8 @@ static inline int _is_in_region(u32_t r_index, u32_t start, u32_t size)
ARM_MPU_DEV->rnr = r_index;
r_addr_start = ARM_MPU_DEV->rbar & MPU_RBAR_ADDR_Msk;
r_size_lshift = ((ARM_MPU_DEV->rasr & REGION_SIZE_MASK) >>
REGION_SIZE_OFFSET) + 1;
r_size_lshift = ((ARM_MPU_DEV->rasr & MPU_RASR_SIZE_Msk) >>
MPU_RASR_SIZE_Pos) + 1;
r_addr_end = r_addr_start + (1 << r_size_lshift) - 1;
if (start >= r_addr_start && (start + size - 1) <= r_addr_end) {
@ -223,7 +223,7 @@ static inline int _is_user_accessible_region(u32_t r_index, int write)
u32_t r_ap;
ARM_MPU_DEV->rnr = r_index;
r_ap = ARM_MPU_DEV->rasr & ACCESS_PERMS_MASK;
r_ap = ARM_MPU_DEV->rasr & MPU_RASR_AP_Msk;
/* always return true if this is the thread stack region */
if (_get_region_index_by_type(THREAD_STACK_REGION) == r_index) {
@ -235,7 +235,7 @@ static inline int _is_user_accessible_region(u32_t r_index, int write)
}
/* For all user accessible permissions, their AP[1] bit is l */
return r_ap & (0x2 << ACCESS_PERMS_OFFSET);
return r_ap & (0x2 << MPU_RASR_AP_Pos);
}
/* ARM Core MPU Driver API Implementation for ARM MPU */

14
include/arch/arm/arch.h
View file

@ -247,12 +247,12 @@ extern "C" {
#ifndef _ASMLANGUAGE
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
#define K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS | NOT_EXEC)
#define K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW | NOT_EXEC)
#define K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO | NOT_EXEC)
#define K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA | NOT_EXEC)
#define K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO | NOT_EXEC)
#define K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA | NOT_EXEC)
#define K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO | MPU_RASR_XN_Msk)
#define K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA | MPU_RASR_XN_Msk)
/* Execution-allowed attributes */
#define K_MEM_PARTITION_P_RWX_U_RWX (P_RW_U_RW)
@ -274,7 +274,7 @@ extern "C" {
__is_writable__; \
})
#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
(!((attr) & (NOT_EXEC)))
(!((attr) & (MPU_RASR_XN_Msk)))
#endif /* _ASMLANGUAGE */
#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \

22
include/arch/arm/cortex_m/mpu/arm_mpu.h
View file

@ -36,22 +36,6 @@ struct arm_mpu {
#define ARM_MPU_BASE 0xE000ED90
/* ARM MPU RASR Register */
/* Region enable bit offset */
#define REGION_ENABLE_OFFSET (0)
/* Region enable bit mask */
#define REGION_ENABLE_MASK (0x1 << REGION_ENABLE_OFFSET)
/* Region size bit offset */
#define REGION_SIZE_OFFSET (1)
/* Region size bit mask */
#define REGION_SIZE_MASK (0x1F << REGION_SIZE_OFFSET)
/* Access permissions bit offset */
#define ACCESS_PERMS_OFFSET (24)
/* Access permissions bit mask */
#define ACCESS_PERMS_MASK (0x7 << ACCESS_PERMS_OFFSET)
/* eXecute Never */
#define NOT_EXEC (0x1 << 28)
/* Privileged No Access, Unprivileged No Access */
#define NO_ACCESS (0x0 << 24)
@ -90,10 +74,10 @@ struct arm_mpu {
/* Some helper defines for common regions */
#define REGION_USER_RAM_ATTR(size) \
(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \
NOT_EXEC | size | FULL_ACCESS)
MPU_RASR_XN_Msk | size | FULL_ACCESS)
#define REGION_RAM_ATTR(size) \
(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \
NOT_EXEC | size | P_RW_U_NA)
MPU_RASR_XN_Msk | size | P_RW_U_NA)
#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
#define REGION_FLASH_ATTR(size) \
(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | size | \
@ -143,8 +127,6 @@ struct arm_mpu {
#define REGION_2G (0x1E << 1)
#define REGION_4G (0x1F << 1)
#define REGION_ENABLE (1 << 0)
/* Region definition data structure */
struct arm_mpu_region {
/* Region Base Address */