From 1514c41cd1edc3a0cbf910e2d9b51bda56f870dd Mon Sep 17 00:00:00 2001
From: Bradley Bolen <bbolen@lexmark.com>
Date: Fri, 10 Aug 2018 11:49:06 -0400
Subject: [PATCH] arch: arm: Move Cortex-M specific CPU defines

These defines are specific to the Cortex-M.  Move them to their own
header file to prepare for Cortex-R support.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
---
 include/arch/arm/arch.h           |  1 +
 include/arch/arm/asm_inline_gcc.h |  9 +--------
 include/arch/arm/cortex_m/cpu.h   | 20 ++++++++++++++++++++
 3 files changed, 22 insertions(+), 8 deletions(-)
 create mode 100644 include/arch/arm/cortex_m/cpu.h

diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h
index 9e8bec6c9f6..bbce87d8b48 100644
--- a/include/arch/arm/arch.h
+++ b/include/arch/arm/arch.h
@@ -33,6 +33,7 @@
 #include <arch/arm/asm_inline.h>
 
 #ifdef CONFIG_CPU_CORTEX_M
+#include <arch/arm/cortex_m/cpu.h>
 #include <arch/arm/cortex_m/memory_map.h>
 #endif
 
diff --git a/include/arch/arm/asm_inline_gcc.h b/include/arch/arm/asm_inline_gcc.h
index 9b484305474..148444846cb 100644
--- a/include/arch/arm/asm_inline_gcc.h
+++ b/include/arch/arm/asm_inline_gcc.h
@@ -20,15 +20,8 @@ extern "C" {
  * Include arch/cpu.h instead
  */
 
-#ifdef _ASMLANGUAGE
+#ifndef _ASMLANGUAGE
 
-#define _SCS_BASE_ADDR _PPB_INT_SCS
-#define _SCS_ICSR (_SCS_BASE_ADDR + 0xd04)
-#define _SCS_ICSR_PENDSV (1 << 28)
-#define _SCS_ICSR_UNPENDSV (1 << 27)
-#define _SCS_ICSR_RETTOBASE (1 << 11)
-
-#else /* !_ASMLANGUAGE */
 #include <zephyr/types.h>
 #include <arch/arm/exc.h>
 #include <irq.h>
diff --git a/include/arch/arm/cortex_m/cpu.h b/include/arch/arm/cortex_m/cpu.h
new file mode 100644
index 00000000000..acd27d6f2d6
--- /dev/null
+++ b/include/arch/arm/cortex_m/cpu.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _CORTEX_M_CPU_H
+#define _CORTEX_M_CPU_H
+
+#ifdef _ASMLANGUAGE
+
+#define _SCS_BASE_ADDR _PPB_INT_SCS
+#define _SCS_ICSR (_SCS_BASE_ADDR + 0xd04)
+#define _SCS_ICSR_PENDSV (1 << 28)
+#define _SCS_ICSR_UNPENDSV (1 << 27)
+#define _SCS_ICSR_RETTOBASE (1 << 11)
+
+#endif
+
+#endif