From 14ba292870970d27e501ae9f16433815e97c3810 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 14 Nov 2018 10:20:56 -0500 Subject: [PATCH] xtensa: fix dts_fixup.h with new DT_ prefix This fixes majority of drivers, however we still see build failures with the interrupt handler. Signed-off-by: Anas Nashif --- boards/xtensa/intel_s1000_crb/dts_fixup.h | 14 ++-- soc/xtensa/intel_s1000/dts_fixup.h | 84 +++++++++++------------ 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/boards/xtensa/intel_s1000_crb/dts_fixup.h b/boards/xtensa/intel_s1000_crb/dts_fixup.h index 77f79c186ed..a6006b22b4e 100644 --- a/boards/xtensa/intel_s1000_crb/dts_fixup.h +++ b/boards/xtensa/intel_s1000_crb/dts_fixup.h @@ -7,23 +7,23 @@ /* Board level DTS fixup file */ #define DT_CODEC_I2C_BUS_NAME \ - SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BUS_NAME + DT_SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BUS_NAME #define DT_CODEC_I2C_BUS_ADDR \ - SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BASE_ADDRESS + DT_SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BASE_ADDRESS #define DT_CODEC_NAME \ - SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_LABEL + DT_SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_LABEL #define CONFIG_SPI_NOR_SPI_NAME \ - SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_BUS_NAME + DT_SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_BUS_NAME #define CONFIG_SPI_NOR_SPI_FREQ_0 \ - SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_SPI_MAX_FREQUENCY + DT_SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_SPI_MAX_FREQUENCY #define CONFIG_SPI_NOR_DRV_NAME \ - SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_LABEL + DT_SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_LABEL #define CONFIG_SPI_NOR_SPI_SLAVE \ - SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_BASE_ADDRESS + DT_SNPS_DESIGNWARE_SPI_E000_SPI_FLASH_0_BASE_ADDRESS /* End of Board Level DTS fixup file */ diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index 0cbc131647e..481a3656b0b 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -1,62 +1,62 @@ /* SoC level DTS fixup file */ -#define DT_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS -#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED -#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL -#define DT_UART_NS16550_PORT_0_IRQ ((NS16550_80800_IRQ_0 << 16) | \ - (SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ - (INTEL_CAVS_INTC_78800_IRQ_0 << 0)) +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS +#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED +#define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL +#define DT_UART_NS16550_PORT_0_IRQ ((DT_NS16550_80800_IRQ_0 << 16) | \ + (DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ + (DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0)) -#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80800_IRQ_0_PRIORITY -#define DT_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_80800_IRQ_0_SENSE -#define DT_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY +#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_80800_IRQ_0_PRIORITY +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_80800_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80800_CLOCK_FREQUENCY #define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS #define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024 -#define DT_CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS -#define DT_CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0 -#define DT_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY -#define DT_CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE +#define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_78800_BASE_ADDRESS +#define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_78800_IRQ_0 +#define DT_CAVS_ICTL_0_IRQ_PRI DT_INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_0_IRQ_FLAGS DT_INTEL_CAVS_INTC_78800_IRQ_0_SENSE -#define DT_CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0 -#define DT_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY -#define DT_CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE +#define DT_CAVS_ICTL_1_IRQ DT_INTEL_CAVS_INTC_78810_IRQ_0 +#define DT_CAVS_ICTL_1_IRQ_PRI DT_INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_1_IRQ_FLAGS DT_INTEL_CAVS_INTC_78810_IRQ_0_SENSE -#define DT_CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0 -#define DT_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY -#define DT_CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE +#define DT_CAVS_ICTL_2_IRQ DT_INTEL_CAVS_INTC_78820_IRQ_0 +#define DT_CAVS_ICTL_2_IRQ_PRI DT_INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_2_IRQ_FLAGS DT_INTEL_CAVS_INTC_78820_IRQ_0_SENSE -#define DT_CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0 -#define DT_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY -#define DT_CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE +#define DT_CAVS_ICTL_3_IRQ DT_INTEL_CAVS_INTC_78830_IRQ_0 +#define DT_CAVS_ICTL_3_IRQ_PRI DT_INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_3_IRQ_FLAGS DT_INTEL_CAVS_INTC_78830_IRQ_0_SENSE -#define DT_DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS -#define DT_DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ - (INTEL_CAVS_INTC_78800_IRQ_0 << 0)) -#define DT_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY -#define DT_DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE +#define DT_DW_ICTL_BASE_ADDR DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS +#define DT_DW_ICTL_IRQ ((DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ + (DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0)) +#define DT_DW_ICTL_IRQ_PRI DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY +#define DT_DW_ICTL_IRQ_FLAGS DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE -#define DT_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS -#define DT_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY -#define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL -#define DT_I2C_0_IRQ ((SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \ - (SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ - (INTEL_CAVS_INTC_78800_IRQ_0 << 0)) +#define DT_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS +#define DT_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY +#define CONFIG_I2C_0_NAME DT_SNPS_DESIGNWARE_I2C_80400_LABEL +#define DT_I2C_0_IRQ ((DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \ + (DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ + (DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0)) -#define DT_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE -#define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY +#define DT_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE +#define CONFIG_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY -#define CONFIG_SPI_0_BASE_ADDRESS SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS -#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_E000_LABEL +#define CONFIG_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS +#define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_E000_LABEL -#define CONFIG_SPI_0_IRQ ((SNPS_DESIGNWARE_SPI_E000_IRQ_0 << 16) | \ - (SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ - (INTEL_CAVS_INTC_78800_IRQ_0 << 0)) +#define CONFIG_SPI_0_IRQ ((DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0 << 16) | \ + (DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ + (DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0)) -#define SPI_DW_IRQ_FLAGS SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE +#define SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE -#define CONFIG_SPI_0_IRQ_PRI SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY +#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY /* End of SoC Level DTS fixup file */