michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: stm32l0: add power management support

Browse source 
Add power management support to STM32L0 series.

The SoC have a single stop state that can be used with LPTIM as a system
timer, as well as a standby mode where the system resets on exit.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This commit is contained in:
Fabio Baltieri 2021-05-16 18:19:43 +01:00 • committed by Anas Nashif
commit 13facbefad
3 changed files with 107 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
soc/arm/st_stm32/stm32l0/CMakeLists.txt
View file

@ -4,3 +4,7 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources(
soc.c
)
zephyr_sources_ifdef(CONFIG_PM
power.c
)

8
soc/arm/st_stm32/stm32l0/Kconfig.defconfig.series
View file

@ -12,4 +12,12 @@ source "soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l0*"
config SOC_SERIES
default "stm32l0"
if PM
config PM_DEVICE
default y
config STM32_LPTIM_TIMER
default y
endif # PM
endif # SOC_SERIES_STM32L0X

95
soc/arm/st_stm32/stm32l0/power.c Normal file
View file

@ -0,0 +1,95 @@
/*
* Copyright (c) 2021 Fabio Baltieri
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <pm/pm.h>
#include <soc.h>
#include <init.h>
#include <stm32l0xx_ll_utils.h>
#include <stm32l0xx_ll_bus.h>
#include <stm32l0xx_ll_cortex.h>
#include <stm32l0xx_ll_pwr.h>
#include <stm32l0xx_ll_rcc.h>
#include <stm32l0xx_ll_system.h>
#include <clock_control/clock_stm32_ll_common.h>
#include <logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
/* Select MSI as wake-up system clock if configured, HSI otherwise */
#if STM32_SYSCLK_SRC_MSI
#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_MSI
#else
#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_HSI
#endif
/* Invoke Low Power/System Off specific Tasks */
void pm_power_state_set(struct pm_state_info info)
{
switch (info.state) {
case PM_STATE_SUSPEND_TO_IDLE:
LL_RCC_SetClkAfterWakeFromStop(RCC_STOP_WAKEUPCLOCK_SELECTED);
LL_PWR_ClearFlag_WU();
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP);
LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER);
LL_LPM_EnableDeepSleep();
k_cpu_idle();
break;
case PM_STATE_SOFT_OFF:
LL_PWR_ClearFlag_WU();
LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
LL_LPM_EnableDeepSleep();
k_cpu_idle();
break;
default:
LOG_DBG("Unsupported power state %u", info.state);
break;
}
}
/* Handle SOC specific activity after Low Power Mode Exit */
void pm_power_state_exit_post_ops(struct pm_state_info info)
{
switch (info.state) {
case PM_STATE_SUSPEND_TO_IDLE:
LL_LPM_DisableSleepOnExit();
LL_LPM_EnableSleep();
/* Restore the clock setup. */
stm32_clock_control_init(NULL);
break;
case PM_STATE_SOFT_OFF:
/* Nothing to do. */
break;
default:
LOG_DBG("Unsupported power substate-id %u", info.state);
break;
}
/*
* System is now in active mode. Reenable interrupts which were
* disabled when OS started idling code.
*/
irq_unlock(0);
}
/* Initialize STM32 Power */
static int stm32_power_init(const struct device *dev)
{
ARG_UNUSED(dev);
/* Enable Power clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
#ifdef CONFIG_DEBUG
/* Enable the Debug Module during STOP mode */
LL_DBGMCU_EnableDBGStopMode();
#endif /* CONFIG_DEBUG */
return 0;
}
SYS_INIT(stm32_power_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);