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serial: RV32M1: introduce lpuart driver / DT bindings

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Add a UART driver.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
This commit is contained in:
Michael Scott 2018-11-07 10:13:52 -08:00 • committed by Anas Nashif
commit 13c794bc1c
10 changed files with 599 additions and 0 deletions
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1
drivers/serial/CMakeLists.txt
View file

@ -25,6 +25,7 @@ zephyr_library_sources_if_kconfig(uart_sam0.c)
zephyr_library_sources_if_kconfig(usart_mcux_lpc.c)
zephyr_library_sources_if_kconfig(uart_psoc6.c)
zephyr_library_sources_if_kconfig(uart_pl011.c)
zephyr_library_sources_if_kconfig(uart_rv32m1_lpuart.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)

2
drivers/serial/Kconfig
View file

@ -114,4 +114,6 @@ source "drivers/serial/Kconfig.psoc6"
source "drivers/serial/Kconfig.pl011"
source "drivers/serial/Kconfig.rv32m1_lpuart"
endif

41
drivers/serial/Kconfig.rv32m1_lpuart Normal file
View file

@ -0,0 +1,41 @@
# Kconfig - RV32M1 SDK LPUART
#
# Copyright (c) 2018 Foundries.io
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig UART_RV32M1_LPUART
bool "RV32M1 LPUART driver"
depends on HAS_RV32M1_LPUART && CLOCK_CONTROL
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
Enable the RV32M1 LPUART driver.
if UART_RV32M1_LPUART
menuconfig UART_RV32M1_LPUART_0
bool "UART 0"
help
Enable UART 0.
menuconfig UART_RV32M1_LPUART_1
bool "UART 1"
depends on RV32M1_INTMUX
help
Enable UART 1.
menuconfig UART_RV32M1_LPUART_2
bool "UART 2"
depends on RV32M1_INTMUX
help
Enable UART 2.
menuconfig UART_RV32M1_LPUART_3
bool "UART 3"
depends on RV32M1_INTMUX
help
Enable UART 3.
endif # UART_RV32M1_LPUART

459
drivers/serial/uart_rv32m1_lpuart.c Normal file
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@ -0,0 +1,459 @@
/*
* Copyright (c) 2018 Foundries.io
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <device.h>
#include <uart.h>
#include <clock_control.h>
#include <fsl_lpuart.h>
#include <soc.h>
struct rv32m1_lpuart_config {
LPUART_Type *base;
char *clock_name;
clock_control_subsys_t clock_subsys;
clock_ip_name_t clock_ip_name;
u32_t clock_ip_src;
u32_t baud_rate;
u8_t hw_flow_control;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
void (*irq_config_func)(struct device *dev);
#endif
};
struct rv32m1_lpuart_data {
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t callback;
void *cb_data;
#endif
};
static int rv32m1_lpuart_poll_in(struct device *dev, unsigned char *c)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t flags = LPUART_GetStatusFlags(config->base);
int ret = -1;
if (flags & kLPUART_RxDataRegFullFlag) {
*c = LPUART_ReadByte(config->base);
ret = 0;
}
return ret;
}
static void rv32m1_lpuart_poll_out(struct device *dev, unsigned char c)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
while (!(LPUART_GetStatusFlags(config->base)
& kLPUART_TxDataRegEmptyFlag))
;
LPUART_WriteByte(config->base, c);
}
static int rv32m1_lpuart_err_check(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t flags = LPUART_GetStatusFlags(config->base);
int err = 0;
if (flags & kLPUART_RxOverrunFlag) {
err |= UART_ERROR_OVERRUN;
}
if (flags & kLPUART_ParityErrorFlag) {
err |= UART_ERROR_PARITY;
}
if (flags & kLPUART_FramingErrorFlag) {
err |= UART_ERROR_FRAMING;
}
LPUART_ClearStatusFlags(config->base, kLPUART_RxOverrunFlag |
kLPUART_ParityErrorFlag |
kLPUART_FramingErrorFlag);
return err;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static int rv32m1_lpuart_fifo_fill(struct device *dev, const u8_t *tx_data,
int len)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u8_t num_tx = 0;
while ((len - num_tx > 0) &&
(LPUART_GetStatusFlags(config->base)
& kLPUART_TxDataRegEmptyFlag)) {
LPUART_WriteByte(config->base, tx_data[num_tx++]);
}
return num_tx;
}
static int rv32m1_lpuart_fifo_read(struct device *dev, u8_t *rx_data,
const int len)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u8_t num_rx = 0;
while ((len - num_rx > 0) &&
(LPUART_GetStatusFlags(config->base)
& kLPUART_RxDataRegFullFlag)) {
rx_data[num_rx++] = LPUART_ReadByte(config->base);
}
return num_rx;
}
static void rv32m1_lpuart_irq_tx_enable(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
LPUART_EnableInterrupts(config->base, mask);
}
static void rv32m1_lpuart_irq_tx_disable(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
LPUART_DisableInterrupts(config->base, mask);
}
static int rv32m1_lpuart_irq_tx_complete(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t flags = LPUART_GetStatusFlags(config->base);
return (flags & kLPUART_TxDataRegEmptyFlag) != 0;
}
static int rv32m1_lpuart_irq_tx_ready(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
return (LPUART_GetEnabledInterrupts(config->base) & mask)
&& rv32m1_lpuart_irq_tx_complete(dev);
}
static void rv32m1_lpuart_irq_rx_enable(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_RxDataRegFullInterruptEnable;
LPUART_EnableInterrupts(config->base, mask);
}
static void rv32m1_lpuart_irq_rx_disable(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_RxDataRegFullInterruptEnable;
LPUART_DisableInterrupts(config->base, mask);
}
static int rv32m1_lpuart_irq_rx_full(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t flags = LPUART_GetStatusFlags(config->base);
return (flags & kLPUART_RxDataRegFullFlag) != 0;
}
static int rv32m1_lpuart_irq_rx_ready(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_RxDataRegFullInterruptEnable;
return (LPUART_GetEnabledInterrupts(config->base) & mask)
&& rv32m1_lpuart_irq_rx_full(dev);
}
static void rv32m1_lpuart_irq_err_enable(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_NoiseErrorInterruptEnable |
kLPUART_FramingErrorInterruptEnable |
kLPUART_ParityErrorInterruptEnable;
LPUART_EnableInterrupts(config->base, mask);
}
static void rv32m1_lpuart_irq_err_disable(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
u32_t mask = kLPUART_NoiseErrorInterruptEnable |
kLPUART_FramingErrorInterruptEnable |
kLPUART_ParityErrorInterruptEnable;
LPUART_DisableInterrupts(config->base, mask);
}
static int rv32m1_lpuart_irq_is_pending(struct device *dev)
{
return (rv32m1_lpuart_irq_tx_ready(dev)
|| rv32m1_lpuart_irq_rx_ready(dev));
}
static int rv32m1_lpuart_irq_update(struct device *dev)
{
return 1;
}
static void rv32m1_lpuart_irq_callback_set(struct device *dev,
uart_irq_callback_user_data_t cb,
void *cb_data)
{
struct rv32m1_lpuart_data *data = dev->driver_data;
data->callback = cb;
data->cb_data = cb_data;
}
static void rv32m1_lpuart_isr(void *arg)
{
struct device *dev = arg;
struct rv32m1_lpuart_data *data = dev->driver_data;
if (data->callback) {
data->callback(data->cb_data);
}
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static int rv32m1_lpuart_init(struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config->config_info;
lpuart_config_t uart_config;
struct device *clock_dev;
u32_t clock_freq;
/* set clock source */
/* TODO: Don't change if another core has configured */
CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
clock_dev = device_get_binding(config->clock_name);
if (clock_dev == NULL) {
return -EINVAL;
}
if (clock_control_get_rate(clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
LPUART_GetDefaultConfig(&uart_config);
uart_config.enableTx = true;
uart_config.enableRx = true;
if (config->hw_flow_control) {
uart_config.enableRxRTS = true;
uart_config.enableTxCTS = true;
}
uart_config.baudRate_Bps = config->baud_rate;
LPUART_Init(config->base, &uart_config, clock_freq);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
config->irq_config_func(dev);
#endif
return 0;
}
static const struct uart_driver_api rv32m1_lpuart_driver_api = {
.poll_in = rv32m1_lpuart_poll_in,
.poll_out = rv32m1_lpuart_poll_out,
.err_check = rv32m1_lpuart_err_check,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = rv32m1_lpuart_fifo_fill,
.fifo_read = rv32m1_lpuart_fifo_read,
.irq_tx_enable = rv32m1_lpuart_irq_tx_enable,
.irq_tx_disable = rv32m1_lpuart_irq_tx_disable,
.irq_tx_complete = rv32m1_lpuart_irq_tx_complete,
.irq_tx_ready = rv32m1_lpuart_irq_tx_ready,
.irq_rx_enable = rv32m1_lpuart_irq_rx_enable,
.irq_rx_disable = rv32m1_lpuart_irq_rx_disable,
.irq_rx_ready = rv32m1_lpuart_irq_rx_ready,
.irq_err_enable = rv32m1_lpuart_irq_err_enable,
.irq_err_disable = rv32m1_lpuart_irq_err_disable,
.irq_is_pending = rv32m1_lpuart_irq_is_pending,
.irq_update = rv32m1_lpuart_irq_update,
.irq_callback_set = rv32m1_lpuart_irq_callback_set,
#endif
};
#ifdef CONFIG_UART_RV32M1_LPUART_0
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_0(struct device *dev);
#endif
static const struct rv32m1_lpuart_config rv32m1_lpuart_0_config = {
.base = (LPUART_Type *)UART_0_BASE_ADDRESS,
.clock_name = UART_0_CLOCK_CONTROLLER,
.clock_subsys = (clock_control_subsys_t)UART_0_CLOCK_NAME,
.clock_ip_name = kCLOCK_Lpuart0,
.clock_ip_src = kCLOCK_IpSrcFircAsync,
.baud_rate = UART_0_CURRENT_SPEED,
#ifdef UART_0_HW_FLOW_CONTROL
.hw_flow_control = UART_0_HW_FLOW_CONTROL,
#endif
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = rv32m1_lpuart_config_func_0,
#endif
};
static struct rv32m1_lpuart_data rv32m1_lpuart_0_data;
DEVICE_AND_API_INIT(uart_0, UART_0_LABEL,
&rv32m1_lpuart_init,
&rv32m1_lpuart_0_data, &rv32m1_lpuart_0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&rv32m1_lpuart_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_0(struct device *dev)
{
IRQ_CONNECT(UART_0_IRQ, UART_0_IRQ_PRI, rv32m1_lpuart_isr,
DEVICE_GET(uart_0), 0);
irq_enable(UART_0_IRQ);
}
#endif
#endif /* CONFIG_UART_RV32M1_LPUART_0 */
#ifdef CONFIG_UART_RV32M1_LPUART_1
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_1(struct device *dev);
#endif
static const struct rv32m1_lpuart_config rv32m1_lpuart_1_config = {
.base = (LPUART_Type *)UART_1_BASE_ADDRESS,
.clock_name = UART_1_CLOCK_CONTROLLER,
.clock_subsys = (clock_control_subsys_t)UART_1_CLOCK_NAME,
.clock_ip_name = kCLOCK_Lpuart1,
.clock_ip_src = kCLOCK_IpSrcFircAsync,
.baud_rate = UART_1_CURRENT_SPEED,
#ifdef UART_1_HW_FLOW_CONTROL
.hw_flow_control = UART_1_HW_FLOW_CONTROL,
#endif
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = rv32m1_lpuart_config_func_1,
#endif
};
static struct rv32m1_lpuart_data rv32m1_lpuart_1_data;
DEVICE_AND_API_INIT(uart_1, UART_1_LABEL,
&rv32m1_lpuart_init,
&rv32m1_lpuart_1_data, &rv32m1_lpuart_1_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&rv32m1_lpuart_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_1(struct device *dev)
{
IRQ_CONNECT(UART_1_IRQ, UART_1_IRQ_PRI, rv32m1_lpuart_isr,
DEVICE_GET(uart_1), 0);
irq_enable(UART_1_IRQ);
}
#endif
#endif /* CONFIG_UART_RV32M1_LPUART_1 */
#ifdef CONFIG_UART_RV32M1_LPUART_2
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_2(struct device *dev);
#endif
static const struct rv32m1_lpuart_config rv32m1_lpuart_2_config = {
.base = (LPUART_Type *)UART_2_BASE_ADDRESS,
.clock_name = UART_2_CLOCK_CONTROLLER,
.clock_subsys = (clock_control_subsys_t)UART_2_CLOCK_NAME,
.clock_ip_name = kCLOCK_Lpuart2,
.clock_ip_src = kCLOCK_IpSrcFircAsync,
.baud_rate = UART_2_CURRENT_SPEED,
#ifdef UART_2_HW_FLOW_CONTROL
.hw_flow_control = UART_2_HW_FLOW_CONTROL,
#endif
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = rv32m1_lpuart_config_func_2,
#endif
};
static struct rv32m1_lpuart_data rv32m1_lpuart_2_data;
DEVICE_AND_API_INIT(uart_2, UART_2_LABEL,
&rv32m1_lpuart_init,
&rv32m1_lpuart_2_data, &rv32m1_lpuart_2_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&rv32m1_lpuart_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_2(struct device *dev)
{
IRQ_CONNECT(UART_2_IRQ, UART_2_IRQ_PRI, rv32m1_lpuart_isr,
DEVICE_GET(uart_2), 0);
irq_enable(UART_2_IRQ);
}
#endif
#endif /* CONFIG_UART_RV32M1_LPUART_2 */
#ifdef CONFIG_UART_RV32M1_LPUART_3
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_3(struct device *dev);
#endif
static const struct rv32m1_lpuart_config rv32m1_lpuart_3_config = {
.base = (LPUART_Type *)UART_3_BASE_ADDRESS,
.clock_name = UART_3_CLOCK_CONTROLLER,
.clock_subsys = (clock_control_subsys_t)UART_3_CLOCK_NAME,
.clock_ip_name = kCLOCK_Lpuart3,
.clock_ip_src = kCLOCK_IpSrcFircAsync,
.baud_rate = UART_3_CURRENT_SPEED,
#ifdef UART_3_HW_FLOW_CONTROL
.hw_flow_control = UART_3_HW_FLOW_CONTROL,
#endif
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = rv32m1_lpuart_config_func_3,
#endif
};
static struct rv32m1_lpuart_data rv32m1_lpuart_3_data;
DEVICE_AND_API_INIT(uart_3, UART_3_LABEL,
&rv32m1_lpuart_init,
&rv32m1_lpuart_3_data, &rv32m1_lpuart_3_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&rv32m1_lpuart_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void rv32m1_lpuart_config_func_3(struct device *dev)
{
IRQ_CONNECT(UART_3_IRQ, UART_3_IRQ_PRI, rv32m1_lpuart_isr,
DEVICE_GET(uart_3), 0);
irq_enable(UART_3_IRQ);
}
#endif
#endif /* CONFIG_UART_RV32M1_LPUART_3 */

38
dts/bindings/serial/openisa,rv32m1-lpuart.yaml Normal file
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@ -0,0 +1,38 @@
---
title: OpenISA LPUART
version: 0.1
description: >
This binding gives a base representation of the OpenISA LPUART
inherits:
!include uart.yaml
properties:
compatible:
constraint: "openisa,rv32m1-lpuart"
reg:
type: array
description: mmio register space
generation: define
category: required
interrupts:
type: array
category: required
description: required interrupts
generation: define
pinctrl-*:
type: array
category: optional
description: pinmux information for RX, TX, CTS, RTS
generation: structures
hw-flow-control:
type: boolean
category: optional
description: use hw flow control
generation: define
...

44
dts/riscv32/rv32m1_ri5cy.dtsi
View file

@ -25,6 +25,10 @@
gpio-c = &gpioc;
gpio-d = &gpiod;
gpio-e = &gpioe;
uart-0 = &uart0;
uart-1 = &uart1;
uart-2 = &uart2;
uart-3 = &uart3;
};
cpus {
@ -200,5 +204,45 @@
#gpio-cells = <2>;
clocks = <&pcc1 0x3c>;
};
uart0: lpuart@40042000 {
compatible = "openisa,rv32m1-lpuart";
reg = <0x40042000 0x2c>;
interrupt-parent = <&event>;
interrupts = <17>;
clocks = <&pcc0 0x108>;
label = "UART_0";
status = "disabled";
};
uart1: lpuart@40043000 {
compatible = "openisa,rv32m1-lpuart";
reg = <0x40043000 0x2c>;
interrupt-parent = <&intmux>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 13)>;
clocks = <&pcc0 0x10c>;
label = "UART_1";
status = "disabled";
};
uart2: lpuart@40044000 {
compatible = "openisa,rv32m1-lpuart";
reg = <0x40044000 0x2c>;
interrupt-parent = <&intmux>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 14)>;
clocks = <&pcc0 0x110>;
label = "UART_2";
status = "disabled";
};
uart3: lpuart@41036000 {
compatible = "openisa,rv32m1-lpuart";
reg = <0x41036000 0x2c>;
interrupt-parent = <&intmux>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 26)>;
clocks = <&pcc0 0xd8>;
label = "UART_3";
status = "disabled";
};
};
};

5
ext/hal/openisa/vega_sdk_riscv/Kconfig
View file

@ -5,3 +5,8 @@
menuconfig VEGA_SDK_HAL
bool "RV32M1 VEGA SDK support"
depends on SOC_OPENISA_RV32M1_RISCV32
config HAS_RV32M1_LPUART
bool
help
Set if the low power uart (LPUART) module is present in the SoC.

1
ext/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/CMakeLists.txt
View file

@ -1,3 +1,4 @@
zephyr_include_directories(.)
zephyr_sources(fsl_clock.c)
zephyr_sources_ifdef(CONFIG_UART_RV32M1_LPUART fsl_lpuart.c)

7
soc/riscv32/openisa_rv32m1/Kconfig.defconfig
View file

@ -177,4 +177,11 @@ config GPIO_RV32M1
endif # GPIO
if SERIAL
config UART_RV32M1_LPUART
def_bool y
endif # SERIAL
endif # SOC_OPENISA_RV32M1_RISCV32

1
soc/riscv32/openisa_rv32m1/Kconfig.soc
View file

@ -12,6 +12,7 @@ config SOC_OPENISA_RV32M1_RISCV32
# (We can't make it a 'depends on' without causing a dependency loop).
select XIP
select HAS_DTS
select HAS_RV32M1_LPUART
select ATOMIC_OPERATIONS_C
select VEGA_SDK_HAL
select RISCV_SOC_INTERRUPT_INIT