Add PCI legacy bridge device driver
PCI legacy bridge is a device connected to PCI bus and allowing to program the routes from interrupt pins to IRQ numbers. Change-Id: I129719d71f958bbf5ad8c5c9949dcea93d94b89d Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
This commit is contained in:
Dmitriy Korovkin
Anas Nashif
parent
30e10c6ee6
commit
13b3e2a127
4 changed files with 256 additions and 0 deletions
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@ -52,6 +52,36 @@ config PCI_ENUMERATION
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statically set in every relevant driver's configuration, it
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might be wise to disable this option to remove useless code.
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config PCI_LEGACY_BRIDGE
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bool
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prompt "PCI legacy bridge device support"
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depends on PCI
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default n
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help
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This option adds support for PCI legacy bridge device, that
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allows direct setup of the PCI interrupt pin to IRQ number
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mapping.
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config PCI_LEGACY_BRIDGE_BUS
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int "PCI Legacy Bridge Bus number"
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depends on PCI_LEGACY_BRIDGE
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default 0
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config PCI_LEGACY_BRIDGE_DEV
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int "PCI Legacy Bridge Device number"
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depends on PCI_LEGACY_BRIDGE
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default 0
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config PCI_LEGACY_BRIDGE_VENDOR_ID
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hex "PCI Legacy Bridge Vendor ID"
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depends on PCI_LEGACY_BRIDGE
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default 0
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config PCI_LEGACY_BRIDGE_DEVICE_ID
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hex "PCI Legacy Bridge Device ID"
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depends on PCI_LEGACY_BRIDGE
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default 0
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config PCI_DEBUG
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bool
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prompt "Enable PCI debugging"
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@ -1 +1,2 @@
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obj-$(CONFIG_PCI) = pci.o pci_config.o pci_interface.o
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obj-$(CONFIG_PCI_LEGACY_BRIDGE) += pci_legacy_bridge.o
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220
drivers/pci/pci_legacy_bridge.c
Normal file
220
drivers/pci/pci_legacy_bridge.c
Normal file
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@ -0,0 +1,220 @@
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/* pci_legacy_bridge.c - PCI legacy bridge device driver */
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/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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Module provides routines for utilizing the PCI legacy bridge, including
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detection of the bridge and using the bridge to configure the routing between
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PCI interrupt pins and IRQs.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <drivers/pci/pci_mgr.h>
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#include <drivers/pci/pci.h>
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#include <board.h>
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#define PCI_LEGACY_BRIDGE_REG (0xF0 / 4) /* RCBA offset in 32-bit words */
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#define PCI_ADDR_IRQAGENT0 0x3140
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#define PCI_ADDR_IRQAGENT1 0x3142
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#define PCI_ADDR_IRQAGENT2 0x3144
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#define PCI_ADDR_IRQAGENT3 0x3146
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/**
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*
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* @brief Return the address mask for the specified root complex
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*
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* The routine checks for the memory present at the specified register
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* and fills in base address mask.
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* Routine should be called in single thread mode during the system
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* initialization.
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*
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* @param pci_ctrl_addr PCI device configuration register address
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* @param mask Pointer to the base address mask
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*
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* @return 0 if root complex is implemented, -1 if not.
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*/
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static int pci_rcba_mask_get(union pci_addr_reg pci_ctrl_addr,
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uint32_t *mask)
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{
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uint32_t old_value;
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/* save the current setting */
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(old_value),
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&old_value);
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/* write to the RCBA to see how large it is */
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pci_write(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(uint32_t),
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0xffffffff);
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(*mask),
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mask);
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/* put back the old configuration */
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pci_write(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(old_value),
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old_value);
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/* check if this RCBA is implemented */
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if (*mask != 0xffffffff && *mask != 0) {
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/* clear the least address unrelated bit */
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*mask &= ~0x01;
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return 0;
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}
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/* RCBA not supported */
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return -1;
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}
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/**
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*
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* @brief Retrieves the device information for the PCI legacy bridge, if present
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*
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* @param dev_info device information structure that the routine fills in
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*
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* @return 0 if legacy bridge is detected and -1 otherwise
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*/
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int pci_legacy_bridge_detect(struct pci_dev_info *dev_info)
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{
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union pci_addr_reg pci_ctrl_addr;
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static union pci_dev pci_dev_header;
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uint32_t pci_data; /* temporary data to read */
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uint32_t rcba; /* root complex base address */
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uint32_t rcba_mask; /* bits set for RCBA */
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/* initialise the PCI controller address register value */
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pci_ctrl_addr.value = 0;
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pci_ctrl_addr.field.bus = CONFIG_PCI_LEGACY_BRIDGE_BUS;
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pci_ctrl_addr.field.device = CONFIG_PCI_LEGACY_BRIDGE_DEV;
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/* verify first if there is a valid device at this point */
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pci_ctrl_addr.field.func = 0;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(pci_data),
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&pci_data);
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if (pci_data == 0xffffffff) {
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return -1;
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}
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/* get the PCI header from the device */
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pci_header_get(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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&pci_dev_header);
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if (pci_dev_header.field.vendor_id != CONFIG_PCI_LEGACY_BRIDGE_VENDOR_ID ||
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pci_dev_header.field.device_id != CONFIG_PCI_LEGACY_BRIDGE_DEVICE_ID) {
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return -1;
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}
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pci_ctrl_addr.field.reg = PCI_LEGACY_BRIDGE_REG;
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/* read RCBA PCI register */
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(rcba),
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&rcba);
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if (pci_rcba_mask_get(pci_ctrl_addr, &rcba_mask) != 0) {
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return -1;
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}
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dev_info->addr = rcba & rcba_mask;
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if (dev_info->addr != 0) {
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/* calculate the size of the root complex memory required */
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dev_info->size = 1 << (find_lsb_set(rcba_mask) - 1);
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}
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dev_info->irq = -1;
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dev_info->bus = CONFIG_PCI_LEGACY_BRIDGE_BUS;
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dev_info->dev = CONFIG_PCI_LEGACY_BRIDGE_DEV;
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dev_info->function = 0;
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dev_info->mem_type = BAR_SPACE_MEM;
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dev_info->class = pci_dev_header.field.class;
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dev_info->bar = 0;
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dev_info->vendor_id = pci_dev_header.field.vendor_id;
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dev_info->device_id = pci_dev_header.field.device_id;
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return 0;
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}
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/**
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*
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* @brief Configures the route from INTx to IRQx on specified I/O block
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*
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* I/O block 0 includes devices connected to PCIe, I/O block 1 includes
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* UART, SPI, GPIO, I2C
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*
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* @param dev_info device information structure that the routine fills in
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* @param io_block_num number on I/O block
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* @param pci_interrupt_pin PCI interrupt pin
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* @param irq_number IRQ number that corresponds the PCI interrupt pin
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*
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* @return N/A
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*/
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void pci_legacy_bridge_configure(struct pci_dev_info *dev_info,
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int io_block_num,
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int pci_interrupt_pin,
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int irq_number)
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{
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uint32_t addr = (io_block_num == 0) ? PCI_ADDR_IRQAGENT1 :
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PCI_ADDR_IRQAGENT3;
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/*
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* Each interrupt queue agent register in PCI legacy
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* bridge has the following format:
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* Bits 15:12 indicates which IRQ is used for INTD. Valid numbers are
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* 0-7, which corresponds IRQ 16 - IRQ 23
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* Bits 11:8 indicates which IRQ is used for INTC.
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* Bits 7:4 indicates which IRQ is used for INTB.
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* Bits 3:0 indicates which IRQ is used for INTA.
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*/
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int offset = (pci_interrupt_pin - 1) * 4;
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uint16_t irq_routing = sys_read16(dev_info->addr + addr);
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irq_routing &= ~(0x0f << offset);
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irq_routing |= (irq_number - NUM_STD_IRQS) << offset;
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sys_write16(irq_routing, dev_info->addr + addr);
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}
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@ -78,6 +78,11 @@ static inline int pci_bus_scan(struct pci_dev_info *dev_info)
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#endif /* CONFIG_PCI_ENUMERATION */
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void pci_enable_regs(struct pci_dev_info *dev_info);
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int pci_legacy_bridge_detect(struct pci_dev_info *dev_info);
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void pci_legacy_bridge_configure(struct pci_dev_info *dev_info,
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int io_block_num,
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int pci_interrupt_pin,
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int irq_number);
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#ifdef CONFIG_PCI_DEBUG
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extern void pci_show(struct pci_dev_info *dev_info);
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