From 13a59fb85532197a02cd8b4112a0da47ae924bc7 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Mon, 2 Sep 2024 14:45:05 +0200 Subject: [PATCH] soc: esp32s3: ESP WiFi heap Provide symbols for the creation of dynamic memory pool. Fix static allocations size check. Signed-off-by: Marek Matej --- soc/espressif/esp32s3/default.ld | 28 ++++++++----------------- soc/espressif/esp32s3/default_appcpu.ld | 12 ++++++++--- soc/espressif/esp32s3/memory.h | 4 ++++ 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld index 7806ab16441..6b9c0ccbc66 100644 --- a/soc/espressif/esp32s3/default.ld +++ b/soc/espressif/esp32s3/default.ld @@ -101,7 +101,7 @@ MEMORY ENTRY(CONFIG_KERNEL_ENTRY) /* Used as a pointer to the heap end */ -_heap_sentry = DRAM_BUFFERS_START; +_heap_sentry = DRAM_RESERVED_START; SECTIONS { @@ -689,14 +689,6 @@ SECTIONS _data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - .dram0.noinit (NOLOAD): - { - . = ALIGN(4); - *(.noinit) - *(.noinit.*) - . = ALIGN(4) ; - } GROUP_LINK_IN(RAMABLE_REGION) - /* Shared RAM */ .dram0.bss (NOLOAD) : { @@ -729,18 +721,19 @@ SECTIONS __bss_end = ABSOLUTE(.); } GROUP_LINK_IN(RAMABLE_REGION) - .dram0.heap_start (NOLOAD) : + .dram0.noinit (NOLOAD): { - . = ALIGN (8); - /* Lowest possible start address for the heap */ - _heap_start = ABSOLUTE(.); + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4) ; } GROUP_LINK_IN(RAMABLE_REGION) /* Provide total SRAM usage, including IRAM and DRAM */ _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; #include - ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + ASSERT(((_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") /* --- END OF DRAM --- */ @@ -906,6 +899,7 @@ SECTIONS #endif /* CONFIG_ESP_SPIRAM */ + /* --- XTENSA GLUE AND DEBUG BEGIN --- */ #ifdef CONFIG_GEN_ISR_TABLES #include @@ -949,11 +943,7 @@ SECTIONS } -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), - "IRAM0 segment data does not fit.") - -ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), - "DRAM segment data does not fit.") + /* --- XTENSA GLUE AND DEBUG END --- */ #if defined(CONFIG_ESP_SPIRAM) ASSERT(((_ext_ram_bss_end - _ext_ram_bss_start) <= CONFIG_ESP_SPIRAM_SIZE), diff --git a/soc/espressif/esp32s3/default_appcpu.ld b/soc/espressif/esp32s3/default_appcpu.ld index bfdaefac078..4641540db75 100644 --- a/soc/espressif/esp32s3/default_appcpu.ld +++ b/soc/espressif/esp32s3/default_appcpu.ld @@ -12,6 +12,8 @@ #define SRAM_DIRAM_I_START 0x40378000 #define SRAM_IRAM_END 0x403BA000 #define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) +#define DRAM_RESERVED_START 0x3fce9704 +#define IRAM_DRAM_OFFSET 0x6f0000 #define SRAM_DRAM_START 0x3FC88000 #define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) @@ -34,6 +36,9 @@ MEMORY /* Default entry point: */ ENTRY(__app_cpu_start) +/* Used as a pointer to the heap end */ +_heap_sentry = DRAM_RESERVED_START; + SECTIONS { #include @@ -259,9 +264,6 @@ SECTIONS #include . = ALIGN(4); - _end = ABSOLUTE(.); - _heap_sentry = .; - . = ALIGN(4); __data_end = ABSOLUTE(.); } GROUP_DATA_LINK_IN(RAMABLE_REGION, IRAM_REGION) @@ -290,6 +292,10 @@ SECTIONS __bss_end = ABSOLUTE(.); } GROUP_LINK_IN(RAMABLE_REGION) + /* Provide total SRAM usage, including IRAM and DRAM */ + _image_ram_start = _iram_start - IRAM_DRAM_OFFSET; + #include + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) diff --git a/soc/espressif/esp32s3/memory.h b/soc/espressif/esp32s3/memory.h index 01dfc69fe7d..7df7f26bccb 100644 --- a/soc/espressif/esp32s3/memory.h +++ b/soc/espressif/esp32s3/memory.h @@ -33,11 +33,15 @@ */ #define IRAM_DRAM_OFFSET 0x6f0000 #define DRAM_BUFFERS_START 0x3fcd7e00 +#define DRAM_BUFFERS_END 0x3fce9704 #define DRAM_PROCPU_STACK_START 0x3fce9710 #define DRAM_STACK_START DRAM_PROCPU_STACK_START #define DRAM_APPCPU_STACK_START 0x3fceb710 #define DRAM_ROM_BSS_DATA_START 0x3fcf0000 +/* Set the limit for the application runtime dynamic allocations */ +#define DRAM_RESERVED_START DRAM_BUFFERS_END + /* Base address used for calculating memory layout * counted from Dbus backwards and back to the Ibus */