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it8xxx2: intc: ensure IER disabling to become effective

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We put disabling SOC interrupt enable register (IER) sequence in
between disable and enable core's global interrupt to prevent race
condition.
After core interrupt enable instruction has been executed, the new
configuration of IER has not yet been fully processed due to
asynchronization between core and SOC's source clock.

If SOC interrupt is fired under the above condition, we will get
IRQ number 0 in ISR due to IER disabling taken effect.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2021-09-03 16:02:16 +08:00 • committed by Carles Cufí
commit 13a2e8200e
1 changed files with 6 additions and 0 deletions
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6
drivers/interrupt_controller/intc_ite_it8xxx2.c
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@ -122,6 +122,7 @@ void ite_intc_irq_disable(unsigned int irq)
{ {
uint32_t g, i; uint32_t g, i;
volatile uint8_t *en; volatile uint8_t *en;
volatile uint8_t _ier __unused;
if (irq > CONFIG_NUM_IRQS) { if (irq > CONFIG_NUM_IRQS) {
return; return;
@ -133,6 +134,11 @@ void ite_intc_irq_disable(unsigned int irq)
/* critical section due to run a bit-wise OR operation */ /* critical section due to run a bit-wise OR operation */
unsigned int key = irq_lock(); unsigned int key = irq_lock();
CLEAR_MASK(*en, BIT(i)); CLEAR_MASK(*en, BIT(i));
/*
* This load operation will guarantee the above modification of
* SOC's register can be seen by any following instructions.
*/
_ier = *en;
irq_unlock(key); irq_unlock(key);
} }