From 1397269335eef0c47586a689dd4094ef8b9d734f Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 7 Nov 2018 20:49:44 +0100 Subject: [PATCH] arch: armv7-m: mpu: disable shareable bit in _get_mpu_ram_region_attr() In Zephyr on Cortex-M SoCs with both the ARM MPU and the cache enabled, there are 3 possible states and associated configuration for the RAM cache attributes: - MPU disabled WBWA non-shareable - MPU enabled, background RAM region WBWA non-shareable - MPU enabled, thread RAM region WBWA shareable In practice this means than the thread RAM region toggles from shareable to non-shareable on each context change. However the Cortex-M7 SoC does not support the WBWA shareable configuration and fallback to simpler caching configuration. The Technical Reference Manual states: "By default, only Normal, Non-shareable memory regions can be cached in the RAMs. Caching only takes place if the appropriate cache is enabled and the memory type is cacheable. Shared cacheable memory regions can be cached if CACR.SIWT is set to 1." Similar indications can be found in the documentation from various vendors: ST (AN4838), NXP (AN12042) and Atmel (AN15679). It means that the thread RAM regions are either not cached (CACR.SIWT=0, default) or WBWT cached (CACR.SIWT=1). This causes a performance issue. In addition before switching a region from cached to non-cached and vice-versa, the existing MPU code does not perform cache clean and/or invalidate operations. This might cause data loss or corruption. We should therefore change the RAM cache attributes to make them always consistent. This patches change the thread/application RAM region from WBWA shareable to WBWA non-shareable. This is done for all ARMv7-M SoCs with an ARM MPU, however other SoCs (M0+, M3, M4) do not have cache, so their behaviour should be unchanged. Signed-off-by: Aurelien Jarno --- arch/arm/core/cortex_m/mpu/arm_mpu_v7_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/core/cortex_m/mpu/arm_mpu_v7_internal.h b/arch/arm/core/cortex_m/mpu/arm_mpu_v7_internal.h index 71ff8b5c4ec..0264a40c6b1 100644 --- a/arch/arm/core/cortex_m/mpu/arm_mpu_v7_internal.h +++ b/arch/arm/core/cortex_m/mpu/arm_mpu_v7_internal.h @@ -103,7 +103,7 @@ static inline void _get_mpu_ram_region_attr(arm_mpu_region_attr_t *p_attr, */ (void) base; - p_attr->rasr = _get_region_attr(1, ap, 1, 1, 1, 1, 0, size); + p_attr->rasr = _get_region_attr(1, ap, 1, 1, 1, 0, 0, size); } /**