diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 03dbfc72327..b34df8574e2 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -3,6 +3,7 @@ zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM clock_control_mcux_ccm.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_PCC clock_control_mcux_pcc.c) +zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG clock_control_mcux_scg.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF nrf_power_clock.c) zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_QUARK_SE quark_se_clock_control.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 2cee58bf37e..f63ea225570 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -35,6 +35,8 @@ source "drivers/clock_control/Kconfig.mcux_ccm" source "drivers/clock_control/Kconfig.mcux_pcc" +source "drivers/clock_control/Kconfig.mcux_scg" + source "drivers/clock_control/Kconfig.mcux_sim" source "drivers/clock_control/Kconfig.rv32m1" diff --git a/drivers/clock_control/Kconfig.mcux_scg b/drivers/clock_control/Kconfig.mcux_scg new file mode 100644 index 00000000000..468eaaab402 --- /dev/null +++ b/drivers/clock_control/Kconfig.mcux_scg @@ -0,0 +1,12 @@ +# Kconfig - MCUXpresso SDK SCG +# +# Copyright (c) 2019 Vestas Wind Systems A/S +# +# SPDX-License-Identifier: Apache-2.0 +# + +menuconfig CLOCK_CONTROL_MCUX_SCG + bool "MCUX SCG driver" + depends on HAS_MCUX_SCG + help + Enable support for mcux scg driver. diff --git a/drivers/clock_control/clock_control_mcux_scg.c b/drivers/clock_control/clock_control_mcux_scg.c new file mode 100644 index 00000000000..1b1275fa5b4 --- /dev/null +++ b/drivers/clock_control/clock_control_mcux_scg.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2019 Vestas Wind Systems A/S + * + * Based on clock_control_mcux_sim.c, which is: + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL +#include +LOG_MODULE_REGISTER(clock_control_scg); + +static int mcux_scg_on(struct device *dev, clock_control_subsys_t sub_system) +{ + return 0; +} + +static int mcux_scg_off(struct device *dev, clock_control_subsys_t sub_system) +{ + return 0; +} + +static int mcux_scg_get_rate(struct device *dev, + clock_control_subsys_t sub_system, + u32_t *rate) +{ + clock_name_t clock_name; + + switch ((u32_t) sub_system) { + case KINETIS_SCG_CORESYS_CLK: + clock_name = kCLOCK_CoreSysClk; + break; + case KINETIS_SCG_BUS_CLK: + clock_name = kCLOCK_BusClk; + break; + case KINETIS_SCG_FLEXBUS_CLK: + clock_name = kCLOCK_FlexBusClk; + break; + case KINETIS_SCG_FLASH_CLK: + clock_name = kCLOCK_FlashClk; + break; + case KINETIS_SCG_SOSC_CLK: + clock_name = kCLOCK_ScgSysOscClk; + break; + case KINETIS_SCG_SIRC_CLK: + clock_name = kCLOCK_ScgSircClk; + break; + case KINETIS_SCG_FIRC_CLK: + clock_name = kCLOCK_ScgFircClk; + break; + case KINETIS_SCG_SPLL_CLK: + clock_name = kCLOCK_ScgSysPllClk; + break; + case KINETIS_SCG_SOSC_ASYNC_DIV1_CLK: + clock_name = kCLOCK_ScgSysOscAsyncDiv1Clk; + break; + case KINETIS_SCG_SOSC_ASYNC_DIV2_CLK: + clock_name = kCLOCK_ScgSysOscAsyncDiv2Clk; + break; + case KINETIS_SCG_SIRC_ASYNC_DIV1_CLK: + clock_name = kCLOCK_ScgSircAsyncDiv1Clk; + break; + case KINETIS_SCG_SIRC_ASYNC_DIV2_CLK: + clock_name = kCLOCK_ScgSircAsyncDiv2Clk; + break; + case KINETIS_SCG_FIRC_ASYNC_DIV1_CLK: + clock_name = kCLOCK_ScgFircAsyncDiv1Clk; + break; + case KINETIS_SCG_FIRC_ASYNC_DIV2_CLK: + clock_name = kCLOCK_ScgFircAsyncDiv2Clk; + break; + case KINETIS_SCG_SPLL_ASYNC_DIV1_CLK: + clock_name = kCLOCK_ScgSysPllAsyncDiv1Clk; + break; + case KINETIS_SCG_SPLL_ASYNC_DIV2_CLK: + clock_name = kCLOCK_ScgSysPllAsyncDiv2Clk; + break; + default: + LOG_ERR("Unsupported clock name"); + return -EINVAL; + } + + *rate = CLOCK_GetFreq(clock_name); + return 0; +} + +static int mcux_scg_init(struct device *dev) +{ + return 0; +} + +static const struct clock_control_driver_api mcux_scg_driver_api = { + .on = mcux_scg_on, + .off = mcux_scg_off, + .get_rate = mcux_scg_get_rate, +}; + +DEVICE_AND_API_INIT(mcux_scg, DT_INST_0_NXP_KINETIS_SCG_LABEL, + &mcux_scg_init, + NULL, NULL, + PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, + &mcux_scg_driver_api); diff --git a/dts/arm/nxp/nxp_ke1xf.dtsi b/dts/arm/nxp/nxp_ke1xf.dtsi index 9e46fba199d..f9ba770a357 100644 --- a/dts/arm/nxp/nxp_ke1xf.dtsi +++ b/dts/arm/nxp/nxp_ke1xf.dtsi @@ -61,6 +61,8 @@ compatible = "nxp,kinetis-scg"; reg = <0x40064000 0x1000>; label = "SCG"; + clock-controller; + #clock-cells = <1>; }; pcc: pcc@40065000 { diff --git a/dts/bindings/arm/nxp,kinetis-scg.yaml b/dts/bindings/arm/nxp,kinetis-scg.yaml index 2d1db422cc0..10e1dd1c6e8 100644 --- a/dts/bindings/arm/nxp,kinetis-scg.yaml +++ b/dts/bindings/arm/nxp,kinetis-scg.yaml @@ -142,3 +142,7 @@ properties: description: clockout clock source generation: define category: optional + +"#cells": + - name + - clock \ No newline at end of file diff --git a/ext/hal/nxp/mcux/Kconfig b/ext/hal/nxp/mcux/Kconfig index 85d75f35944..591d3af2245 100644 --- a/ext/hal/nxp/mcux/Kconfig +++ b/ext/hal/nxp/mcux/Kconfig @@ -101,6 +101,12 @@ config HAS_MCUX_RTC help Set if the real time clock (RTC) modules is present in the SoC. +config HAS_MCUX_SCG + bool + help + Set if the system clock generator (SCG) module is present in the + SoC. + config HAS_MCUX_SIM bool help diff --git a/include/dt-bindings/clock/kinetis_scg.h b/include/dt-bindings/clock/kinetis_scg.h index 0e7f1d2f71f..fddd81619ac 100644 --- a/include/dt-bindings/clock/kinetis_scg.h +++ b/include/dt-bindings/clock/kinetis_scg.h @@ -29,4 +29,22 @@ #define KINETIS_SCG_CLKOUT_SRC_FIRC 3U #define KINETIS_SCG_CLKOUT_SRC_SPLL 6U +/* SCG clock controller clock names */ +#define KINETIS_SCG_CORESYS_CLK 0U +#define KINETIS_SCG_BUS_CLK 1U +#define KINETIS_SCG_FLEXBUS_CLK 2U +#define KINETIS_SCG_FLASH_CLK 3U +#define KINETIS_SCG_SOSC_CLK 4U +#define KINETIS_SCG_SIRC_CLK 5U +#define KINETIS_SCG_FIRC_CLK 6U +#define KINETIS_SCG_SPLL_CLK 7U +#define KINETIS_SCG_SOSC_ASYNC_DIV1_CLK 8U +#define KINETIS_SCG_SOSC_ASYNC_DIV2_CLK 9U +#define KINETIS_SCG_SIRC_ASYNC_DIV1_CLK 10U +#define KINETIS_SCG_SIRC_ASYNC_DIV2_CLK 11U +#define KINETIS_SCG_FIRC_ASYNC_DIV1_CLK 12U +#define KINETIS_SCG_FIRC_ASYNC_DIV2_CLK 13U +#define KINETIS_SCG_SPLL_ASYNC_DIV1_CLK 14U +#define KINETIS_SCG_SPLL_ASYNC_DIV2_CLK 15U + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ */