soc: npcx: Add output npcx image in hex format

To support west OpenOCD path image flashing, this generates an npcx hex
image from the npcx BIN image. Moreover, this also changes the name of
npcx output image by CONFIG_KERNEL_BIN_NAME.

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>

boards/arm/npcx7m6fb_evb/board.cmake

@@ -1,14 +1,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
-set(NPCX_IMAGE_FILE  ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}_${BOARD}.bin)
-
-set(TARGET_IMAGE_ADDR  ${CONFIG_FLASH_BASE_ADDRESS})
-set(TARGET_IMAGE_SIZE  ${CONFIG_FLASH_SIZE})
-
 board_set_flasher_ifnset(openocd)
 board_set_debugger_ifnset(openocd)
 
 board_finalize_runner_args(openocd
-  --cmd-load "flash_npcx ${MONITOR_IMAGE_FILE} ${NPCX_IMAGE_FILE} ${TARGET_IMAGE_ADDR} ${TARGET_IMAGE_SIZE}"
+  --cmd-load "npcx_write_image"
-  --cmd-verify "verify_npcx"
+  --cmd-verify "npcx_verify_image"
   )

boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig

@@ -10,6 +10,7 @@ CONFIG_BOARD_NPCX7M6FB_EVB=y
 
 # Enable NPCX firmware header
 CONFIG_NPCX_HEADER=y
+CONFIG_NPCX_IMAGE_OUTPUT_HEX=y
 CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
 CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
 

boards/arm/npcx7m6fb_evb/support/openocd.cfg

@@ -1,4 +1,13 @@
 # script for Nuvoton NPCX Cortex-M4 Series
 
 source [find interface/jlink.cfg]
+transport select swd
 source [find target/npcx.cfg]
+
+proc npcx_write_image {target_image} {
+    flash write_image erase $target_image 0x64000000 ihex
+}
+
+proc npcx_verify_image {target_image} {
+    verify_image $target_image 0x64000000 ihex
+}

boards/arm/npcx9m6f_evb/board.cmake

@@ -1,14 +1,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
-set(NPCX_IMAGE_FILE  ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}_${BOARD}.bin)
-
-set(TARGET_IMAGE_ADDR  ${CONFIG_FLASH_BASE_ADDRESS})
-set(TARGET_IMAGE_SIZE  ${CONFIG_FLASH_SIZE})
-
 board_set_flasher_ifnset(openocd)
 board_set_debugger_ifnset(openocd)
 
 board_finalize_runner_args(openocd
-  --cmd-load "flash_npcx ${MONITOR_IMAGE_FILE} ${NPCX_IMAGE_FILE} ${TARGET_IMAGE_ADDR} ${TARGET_IMAGE_SIZE}"
+  --cmd-load "npcx_write_image"
-  --cmd-verify "verify_npcx"
+  --cmd-verify "npcx_verify_image"
   )

boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig

@@ -10,6 +10,7 @@ CONFIG_BOARD_NPCX9M6F_EVB=y
 
 # Enable NPCX firmware header
 CONFIG_NPCX_HEADER=y
+CONFIG_NPCX_IMAGE_OUTPUT_HEX=y
 CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
 CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
 

boards/arm/npcx9m6f_evb/support/openocd.cfg

@@ -1,4 +1,13 @@
 # script for Nuvoton NPCX Cortex-M4 Series
 
 source [find interface/jlink.cfg]
+transport select swd
 source [find target/npcx.cfg]
+
+proc npcx_write_image {target_image} {
+    flash write_image erase $target_image 0x64000000 ihex
+}
+
+proc npcx_verify_image {target_image} {
+    verify_image $target_image 0x64000000 ihex
+}

soc/arm/nuvoton_npcx/Kconfig

@@ -20,6 +20,21 @@ menuconfig NPCX_HEADER
 
 if NPCX_HEADER
 
+config NPCX_IMAGE_OUTPUT_BIN
+	bool "Build npcx binary in BIN format"
+	default y
+	help
+	  Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory.
+	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
+
+config NPCX_IMAGE_OUTPUT_HEX
+	bool "Build npcx binary in HEX format"
+	depends on NPCX_IMAGE_OUTPUT_BIN
+	help
+	  Build an HEX binary zephyr/zephyr.npcx.hex in the build directory.
+	  This is generated from the npcx BIN image.
+	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
+
 config NPCX_HEADER_CHIP
 	string
 	default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC

soc/arm/nuvoton_npcx/common/CMakeLists.txt

@@ -17,11 +17,12 @@ if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_FIRMWARE_CRC)
     set(NPCX_HEADER_FCRC "-nofcrc")
 endif()
 
-if (DEFINED CONFIG_NPCX_HEADER)
+if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_BIN)
+  set(NPCX_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.bin)
   set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
     COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/ecst/ecst.py
-    -i ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
+    -i ${KERNEL_BIN_NAME}
-    -o ${NPCX_IMAGE_FILE}
+    -o ${NPCX_BIN_NAME}
     ${NPCX_HEADER_HCRC} ${NPCX_HEADER_FCRC}
     -chip ${CONFIG_NPCX_HEADER_CHIP}
     -flashsize ${CONFIG_NPCX_HEADER_FLASH_SIZE}
@@ -29,4 +30,16 @@ if (DEFINED CONFIG_NPCX_HEADER)
     -spimaxclk ${CONFIG_NPCX_HEADER_SPI_MAX_CLOCK}
     -spireadmode ${CONFIG_NPCX_HEADER_SPI_READ_MODE}
   )
+  if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_HEX)
+    set(NPCX_HEX_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.hex)
+    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND $<TARGET_PROPERTY:bintools,elfconvert_command>
+            $<TARGET_PROPERTY:bintools,elfconvert_flag>
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_intarget>binary
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_outtarget>ihex
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${NPCX_BIN_NAME}
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_outfile>${NPCX_HEX_NAME}
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_final>
+    )
+  endif()
 endif()