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doxygen: RETURNS: -> @return

Browse source 
Previous comment style used RETRURNS:, use @return to comply
with javadoc style.

Change-Id: Ib1dffd92da1d97d60063ec5309b08049828f6661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2015-07-01 17:29:04 -04:00
commit 1362e3c162
212 changed files with 1126 additions and 1126 deletions
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22
arch/arc/core/atomic.S
View file

@ -69,7 +69,7 @@ GTEXT(atomic_cas)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -92,7 +92,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_clear)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -141,7 +141,7 @@ SECTION_FUNC(TEXT, atomic_get)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -167,7 +167,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_inc)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -202,7 +202,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_add)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -228,7 +228,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_dec_sub, atomic_dec)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -264,7 +264,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_dec_sub, atomic_sub)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -301,7 +301,7 @@ SECTION_FUNC(TEXT, atomic_nand)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -337,7 +337,7 @@ SECTION_FUNC(TEXT, atomic_and)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -373,7 +373,7 @@ SECTION_FUNC(TEXT, atomic_or)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -409,7 +409,7 @@ SECTION_FUNC(TEXT, atomic_xor)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: 1 if the swap is actually executed, 0 otherwise.
* @return 1 if the swap is actually executed, 0 otherwise.
*
* ERRNO: N/A
*

4
arch/arc/core/context.c
View file

@ -69,7 +69,7 @@ tNANO _nanokernel = {0};
*
* Currently only inserts the new context in the list of active contexts.
*
* RETURNS: N/A
* @return N/A
*/
static ALWAYS_INLINE void context_monitor_init(struct ccs *pCcs /* context */
@ -105,7 +105,7 @@ static ALWAYS_INLINE void context_monitor_init(struct ccs *pCcs /* context */
*
* <options> is currently unused.
*
* RETURNS: N/A
* @return N/A
*/
void _NewContext(

2
arch/arc/core/context_wrapper.S
View file

@ -51,7 +51,7 @@ GTEXT(_context_entry)
* The routine pops parameters for the _context_entry from
* stack frame, prepared by the _NewContext() routine
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _ContextEntryWrapper)

6
arch/arc/core/fast_irq.S
View file

@ -70,7 +70,7 @@ SECTION_VAR(NOINIT, _firq_stack)
*
* Assumption by _isr_demux: r3 is untouched by _firq_enter.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _firq_enter)
@ -101,7 +101,7 @@ SECTION_FUNC(TEXT, _firq_enter)
*
* _firq_exit - work to be done exiting a FIRQ
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _firq_exit)
@ -260,7 +260,7 @@ _firq_no_reschedule:
*
* _firq_stack_setup - install the FIRQ stack in register bank 1
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _firq_stack_setup)

2
arch/arc/core/fatal.c
View file

@ -65,7 +65,7 @@ const NANO_ESF _default_esf = {
* fatal error does not have a hardware generated ESF, the caller should either
* create its own or use a pointer to the global default ESF <_default_esf>.
*
* RETURNS: This function does not return.
* @return This function does not return.
*
* \NOMANUAL
*/

4
arch/arc/core/fault.c
View file

@ -65,7 +65,7 @@
* Dump information regarding the fault when CONFIG_FAULT_DUMP is set to 1
* (short form).
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -92,7 +92,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
* invokes the user provided routine _SysFatalErrorHandler() which is
* responsible for implementing the error handling policy.
*
* RETURNS: This function does not return.
* @return This function does not return.
*
* \NOMANUAL
*/

4
arch/arc/core/ffs.S
View file

@ -55,7 +55,7 @@ GTEXT(nanoFfsLsb)
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: most significant bit set
* @return most significant bit set
*/
SECTION_FUNC(TEXT, nanoFfsMsb)
@ -78,7 +78,7 @@ SECTION_FUNC(TEXT, nanoFfsMsb)
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: least significant bit set
* @return least significant bit set
*/
SECTION_FUNC(TEXT, nanoFfsLsb)

4
arch/arc/core/irq_lock.S
View file

@ -65,7 +65,7 @@
* disable state will be restored when the context is later rescheduled
* for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* @return An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
@ -85,7 +85,7 @@ SECTION_FUNC(TEXT, irq_lock)
*
* This routine can be called from either interrupt, task or fiber level.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

14
arch/arc/core/irq_manage.c
View file

@ -60,7 +60,7 @@
* This routine will hang if <old> is not found in the table and ASSERT_ON is
* enabled.
*
* RETURNS: N/A
* @return N/A
*/
void irq_handler_set(
@ -91,7 +91,7 @@ void irq_handler_set(
* line. After this call, the CPU will receive interrupts for the specified
* <irq>.
*
* RETURNS: N/A
* @return N/A
*/
void irq_enable(unsigned int irq)
@ -108,7 +108,7 @@ void irq_enable(unsigned int irq)
* Disable an interrupt line. After this call, the CPU will stop receiving
* interrupts for the specified <irq>.
*
* RETURNS: N/A
* @return N/A
*/
void irq_disable(unsigned int irq)
@ -128,7 +128,7 @@ void irq_disable(unsigned int irq)
*
* The priority is verified if ASSERT_ON is enabled.
*
* RETURNS: N/A
* @return N/A
*/
void irq_priority_set(
@ -150,7 +150,7 @@ void irq_priority_set(
* Installed in all dynamic interrupt slots at boot time. Throws an error if
* called.
*
* RETURNS: N/A
* @return N/A
*/
#include <misc/printk.h>
@ -172,7 +172,7 @@ void _irq_spurious(void *unused)
* This routine will hang if another ISR was connected for interrupt line <irq>
* and ASSERT_ON is enabled; if ASSERT_ON is disabled, it will fail silently.
*
* RETURNS: the interrupt line number
* @return the interrupt line number
*/
int irq_connect(
@ -194,7 +194,7 @@ int irq_connect(
* replaced by _irq_spurious(). irq_disable() should have been called before
* invoking this routine.
*
* RETURNS: N/A
* @return N/A
*/
void irq_disconnect(unsigned int irq)

4
arch/arc/core/regular_irq.S
View file

@ -59,7 +59,7 @@ GTEXT(_rirq_exit)
*
* Assumption by _isr_demux: r3 is untouched by _rirq_enter.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _rirq_enter)
@ -79,7 +79,7 @@ SECTION_FUNC(TEXT, _rirq_enter)
*
* _rirq_exit - work to be done exiting an IRQ
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _rirq_exit)

2
arch/arc/core/swap.S
View file

@ -75,7 +75,7 @@ GDATA(_nanokernel)
* When _Swap() is invoked, we know the decision to perform a context switch or
* not has already been taken and a context switch must happen.
*
* RETURNS: may contain a return value setup by a call to fiberRtnValueSet()
* @return may contain a return value setup by a call to fiberRtnValueSet()
*
* C function prototype:
*

2
arch/arc/fatal_error.c
View file

@ -76,7 +76,7 @@ static inline void nonEssentialTaskAbort(void)
* implementation to take other actions, such as logging error (or debug)
* information to a persistent repository and/or rebooting the system.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

4
arch/arc/include/nano_private.h
View file

@ -246,7 +246,7 @@ static ALWAYS_INLINE void nanoArchInit(void)
* to <value>. It is assumed that the specified <fiber> is pending, and thus
* the fiber's context is stored in its tCCS structure.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -260,7 +260,7 @@ static ALWAYS_INLINE void fiberRtnValueSet(tCCS *fiber, unsigned int value)
*
* _IS_IN_ISR - indicates if kernel is handling interrupt
*
* RETURNS: 1 if interrupt handler is executed, 0 otherwise
* @return 1 if interrupt handler is executed, 0 otherwise
*
* \NOMANUAL
*/

6
arch/arc/prep_c.c
View file

@ -50,7 +50,7 @@ initialization is performed.
*
* This routine clears the BSS region, so all bytes are 0.
*
* RETURNS: N/A
* @return N/A
*/
static void bssZero(void)
@ -69,7 +69,7 @@ static void bssZero(void)
*
* This routine copies the data section from ROM to RAM.
*
* RETURNS: N/A
* @return N/A
*/
#ifdef CONFIG_XIP
@ -96,7 +96,7 @@ extern FUNC_NORETURN void _Cstart(void);
*
* This routine prepares for the execution of and runs C code.
*
* RETURNS: N/A
* @return N/A
*/
void _PrepC(void)

2
arch/arc/reset.S
View file

@ -57,7 +57,7 @@ GTEXT(__reset)
* When these steps are completed, jump to _PrepC(), which will finish setting
* up the system for running C code.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT,__reset)

8
arch/arm/bsp/CortexM/nmi.c
View file

@ -59,7 +59,7 @@ static _NmiHandler_t handler = _SysNmiOnReset;
* The default handler outputs a error message and reboots the target. It is
* installed by calling _NmiInit();
*
* RETURNS: N/A
* @return N/A
*/
static void _DefaultHandler(void)
@ -76,7 +76,7 @@ static void _DefaultHandler(void)
* that reboots the target. It should be installed after the console is
* initialized.
*
* RETURNS: N/A
* @return N/A
*/
void _NmiInit(void)
@ -92,7 +92,7 @@ void _NmiInit(void)
* that reboots. It should be installed after the console is initialized if it is
* meant to output to the console.
*
* RETURNS: N/A
* @return N/A
*/
void _NmiHandlerSet(void (*pHandler)(void))
@ -107,7 +107,7 @@ void _NmiHandlerSet(void (*pHandler)(void))
*
* Simply call what is installed in 'static void(*handler)(void)'.
*
* RETURNS: N/A
* @return N/A
*/
void __nmi(void)

6
arch/arm/bsp/CortexM/prep_c.c
View file

@ -50,7 +50,7 @@ initialization is performed.
*
* This routine clears the BSS region, so all bytes are 0.
*
* RETURNS: N/A
* @return N/A
*/
static void bssZero(void)
@ -69,7 +69,7 @@ static void bssZero(void)
*
* This routine copies the data section from ROM to RAM.
*
* RETURNS: N/A
* @return N/A
*/
#ifdef CONFIG_XIP
@ -96,7 +96,7 @@ extern FUNC_NORETURN void _Cstart(void);
*
* This routine prepares for the execution of and runs C code.
*
* RETURNS: N/A
* @return N/A
*/
void _PrepC(void)

2
arch/arm/bsp/CortexM/reset.S
View file

@ -67,7 +67,7 @@ GTEXT(__reset)
* When these steps are completed, jump to _PrepC(), which will finish setting
* up the system for running C code.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT,__reset)

4
arch/arm/bsp/CortexM/scb.c
View file

@ -50,7 +50,7 @@ definitions and more complex routines, if needed.
*
* This routine resets the processor.
*
* RETURNS: N/A
* @return N/A
*/
void _ScbSystemReset(void)
@ -74,7 +74,7 @@ void _ScbSystemReset(void)
*
* The number of priorities has to be a power of two, from 1 to 128.
*
* RETURNS: N/A
* @return N/A
*/
void _ScbNumPriGroupSet(unsigned int n /* number of priorities */

2
arch/arm/bsp/sysFatalErrorHandler.c
View file

@ -76,7 +76,7 @@ static inline void nonEssentialTaskAbort(void)
* implementation to take other actions, such as logging error (or debug)
* information to a persistent repository and/or rebooting the system.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

22
arch/arm/core/atomic.S
View file

@ -68,7 +68,7 @@ GTEXT(atomic_cas)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -91,7 +91,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_clear)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -144,7 +144,7 @@ SECTION_FUNC(TEXT, atomic_get)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -170,7 +170,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_inc)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -204,7 +204,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_add)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -230,7 +230,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_decSub, atomic_dec)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -264,7 +264,7 @@ SECTION_SUBSEC_FUNC(TEXT, atomic_decSub, atomic_sub)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -299,7 +299,7 @@ SECTION_FUNC(TEXT, atomic_nand)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -333,7 +333,7 @@ SECTION_FUNC(TEXT, atomic_and)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -367,7 +367,7 @@ SECTION_FUNC(TEXT, atomic_or)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: Contents of <target> before the atomic operation
* @return Contents of <target> before the atomic operation
*
* ERRNO: N/A
*
@ -401,7 +401,7 @@ SECTION_FUNC(TEXT, atomic_xor)
*
* This routine can be used from both task and interrupt level.
*
* RETURNS: 1 if the swap is actually executed, 0 otherwise.
* @return 1 if the swap is actually executed, 0 otherwise.
*
* ERRNO: N/A
*

4
arch/arm/core/basepri.S
View file

@ -69,7 +69,7 @@ GTEXT(irq_unlock)
* This function can be called recursively: it will return a key to return the
* state of interrupt locking to the previous level.
*
* RETURNS: a key to return to the previous interrupt locking level
* @return a key to return to the previous interrupt locking level
*/
SECTION_FUNC(TEXT,irq_lock)
@ -85,7 +85,7 @@ SECTION_FUNC(TEXT,irq_lock)
* Return the state of interrupt locking to a previous level, passed in via the
* <key> parameter, obtained from a previous call to irq_lock().
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT,irq_unlock)

4
arch/arm/core/context.c
View file

@ -59,7 +59,7 @@ tNANO _nanokernel = {0};
*
* Currently only inserts the new context in the list of active contexts.
*
* RETURNS: N/A
* @return N/A
*/
static ALWAYS_INLINE void _context_monitor_init(struct ccs *pCcs /* context */
@ -99,7 +99,7 @@ static ALWAYS_INLINE void _context_monitor_init(struct ccs *pCcs /* context */
*
* <options> is currently unused.
*
* RETURNS: N/A
* @return N/A
*/
void _NewContext(

10
arch/arm/core/cpu_idle.S
View file

@ -63,7 +63,7 @@ GTEXT(nano_cpu_atomic_idle)
* Only called by nanoArchInit(). Sets SEVONPEND bit once for the system's
* duration.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*
@ -84,7 +84,7 @@ SECTION_FUNC(TEXT, _CpuIdleInit)
*
* Returns the nanokernel idle setting, in ticks. Only called by __systick().
*
* RETURNS: the requested number of ticks for the kernel to be idle
* @return the requested number of ticks for the kernel to be idle
*
* C function prototype:
*
@ -102,7 +102,7 @@ SECTION_FUNC(TEXT, _NanoIdleValGet)
*
* Sets the nanokernel idle setting to 0. Only called by __systick().
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*
@ -126,7 +126,7 @@ SECTION_FUNC(TEXT, _NanoIdleValClear)
* '_sys_power_save_flag' variable is non-zero. The ARM 'wfi' instruction
* will be issued, causing a low-power consumption sleep mode.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*
@ -161,7 +161,7 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
* 2) After waking up from the low-power mode, the interrupt lockout state
* must be restored as indicated in the 'imask' input parameter.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*

4
arch/arm/core/exc_exit.S
View file

@ -84,7 +84,7 @@ GDATA(_nanokernel)
* _IntExit();
* }
*
* RETURNS: N/A
* @return N/A
*/
SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _IntExit)
@ -99,7 +99,7 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _IntExit)
*
* See _IntExit().
*
* RETURNS: N/A
* @return N/A
*/
SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _ExcExit)

2
arch/arm/core/fatal.c
View file

@ -75,7 +75,7 @@ const NANO_ESF _default_esf = {0xdeaddead, /* a1 */
* fatal error does not have a hardware generated ESF, the caller should either
* create its own or use a pointer to the global default ESF <_default_esf>.
*
* RETURNS: This function does not return.
* @return This function does not return.
*
* \NOMANUAL
*/

22
arch/arm/core/fault.c
View file

@ -73,7 +73,7 @@ Common fault handler for ARM Cortex-M processors.
* MMFSR: 0x00000000, BFSR: 0x00000082, UFSR: 0x00000000
* BFAR: 0xff001234
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -124,7 +124,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
*
* See _FaultDump() for example.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -143,7 +143,7 @@ static void _FaultContextShow(const NANO_ESF *esf)
*
* See _FaultDump() for example.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -178,7 +178,7 @@ static void _MpuFault(const NANO_ESF *esf,
*
* See _FaultDump() for example.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -219,7 +219,7 @@ static void _BusFault(const NANO_ESF *esf,
*
* See _FaultDump() for example.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -259,7 +259,7 @@ static void _UsageFault(const NANO_ESF *esf)
*
* See _FaultDump() for example.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -287,7 +287,7 @@ static void _HardFault(const NANO_ESF *esf)
*
* See _FaultDump() for example.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -303,7 +303,7 @@ static void _DebugMonitor(const NANO_ESF *esf)
*
* See _FaultDump() for example.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -333,7 +333,7 @@ static void _ReservedException(const NANO_ESF *esf,
* Precise data bus error
* Address: 0xff001234
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -376,7 +376,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
* interrupt was already being handled, it is passed a pointer to both and has
* to find out on which the ESP is present.
*
* RETURNS: This function does not return.
* @return This function does not return.
*
* \NOMANUAL
*/
@ -400,7 +400,7 @@ void _Fault(
*
* Turns on the desired hardware faults.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

4
arch/arm/core/ffs.S
View file

@ -57,7 +57,7 @@ GTEXT(find_first_set)
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: most significant bit set
* @return most significant bit set
*/
SECTION_FUNC(TEXT, find_last_set)
@ -78,7 +78,7 @@ SECTION_FUNC(TEXT, find_last_set)
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: least significant bit set
* @return least significant bit set
*/
SECTION_FUNC(TEXT, find_first_set)

2
arch/arm/core/fiber_abort.c
View file

@ -61,7 +61,7 @@ the PendSV exception.
* - the fiber implicitly aborts by returning from its entry point
* - the fiber encounters a fatal exception
*
* RETURNS: N/A
* @return N/A
*/
void fiber_abort(void)

6
arch/arm/core/gdb_stub.S
View file

@ -70,7 +70,7 @@ _ASM_FILE_PROLOGUE
* - must be called with interrupts locked
* - cannot use r0 without saving it first
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _GdbStubExcEntry)
@ -107,7 +107,7 @@ SECTION_FUNC(TEXT, _GdbStubExcEntry)
* - must be called with interrupts locked
* - cannot use r0 without saving it first
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _GdbStubExcExit)
@ -145,7 +145,7 @@ SECTION_FUNC(TEXT, _GdbStubExcExit)
* This stub must also act as a demuxer that find the running exception and
* invoke the user's real ISR.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _irq_vector_table_entry_with_gdb_stub)

2
arch/arm/core/irq_init.c
View file

@ -53,7 +53,7 @@ the PendSV exception.
* not 0, which they have it set to when coming out of reset. This ensures that
* interrupt locking via BASEPRI works as expected.
*
* RETURNS: N/A
* @return N/A
*/
void _IntLibInit(void)

14
arch/arm/core/irq_manage.c
View file

@ -56,7 +56,7 @@ extern void __reserved(void);
* This routine will hang if <old> is not found in the table and ASSERT_ON is
* enabled.
*
* RETURNS: N/A
* @return N/A
*/
void irq_handler_set(unsigned int irq,
@ -84,7 +84,7 @@ void irq_handler_set(unsigned int irq,
* line. After this call, the CPU will receive interrupts for the specified
* <irq>.
*
* RETURNS: N/A
* @return N/A
*/
void irq_enable(unsigned int irq)
@ -101,7 +101,7 @@ void irq_enable(unsigned int irq)
* Disable an interrupt line. After this call, the CPU will stop receiving
* interrupts for the specified <irq>.
*
* RETURNS: N/A
* @return N/A
*/
void irq_disable(unsigned int irq)
@ -121,7 +121,7 @@ void irq_disable(unsigned int irq)
*
* The priority is verified if ASSERT_ON is enabled.
*
* RETURNS: N/A
* @return N/A
*/
void irq_priority_set(unsigned int irq,
@ -140,7 +140,7 @@ void irq_priority_set(unsigned int irq,
*
* See __reserved().
*
* RETURNS: N/A
* @return N/A
*/
void _irq_spurious(void *unused)
@ -159,7 +159,7 @@ void _irq_spurious(void *unused)
* This routine will hang if another ISR was connected for interrupt line <irq>
* and ASSERT_ON is enabled; if ASSERT_ON is disabled, it will fail silently.
*
* RETURNS: the interrupt line number
* @return the interrupt line number
*/
int irq_connect(unsigned int irq,
@ -180,7 +180,7 @@ int irq_connect(unsigned int irq,
* the latter is replaced by _irq_spurious(). irq_disable() should have
* been called before invoking this routine.
*
* RETURNS: N/A
* @return N/A
*/
void irq_disconnect(unsigned int irq)

2
arch/arm/core/isr_wrapper.S
View file

@ -64,7 +64,7 @@ GTEXT(_IntExit)
* pends the PendSV exception if so: the latter will perform the context switch
* itself.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _isr_wrapper)

4
arch/arm/core/swap.S
View file

@ -153,7 +153,7 @@ SECTION_FUNC(TEXT, __pendsv)
* The service call (svc) is only used in _Swap() to enter handler mode so we
* can go through the PendSV exception to perform a context switch.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, __svc)
@ -203,7 +203,7 @@ SECTION_FUNC(TEXT, __svc)
* outgoing context. This is all performed by the hardware, which stores it in
* its exception stack frame, created when handling the svc exception.
*
* RETURNS: may contain a return value setup by a call to fiberRtnValueSet()
* @return may contain a return value setup by a call to fiberRtnValueSet()
*
* C function prototype:
*

2
arch/arm/core/task_abort.c
View file

@ -62,7 +62,7 @@ static struct k_args cmd_packet;
* - the task implicitly aborts by returning from its entry point
* - the task encounters a fatal exception
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

6
arch/arm/fsl_frdm_k64f/system.c
View file

@ -106,7 +106,7 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
* PLL Bypassed External (PBE) modes to get to the desired
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system clock.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -253,7 +253,7 @@ static void clkInit(void)
*
* Only used for debugging.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -306,7 +306,7 @@ static void consoleInit(void)
* Kinetis UART device driver.
* Also initialize the timer device driver, if required.
*
* RETURNS: N/A
* @return N/A
*/
void _InitHardware(void)

2
arch/arm/fsl_frdm_k64f/wdog.S
View file

@ -59,7 +59,7 @@ GTEXT(_WdogInit)
*
* This routine will disable the watchdog timer.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT,_WdogInit)

4
arch/arm/include/CortexM/asm_inline_gcc.h
View file

@ -46,7 +46,7 @@
*
* Obtain and return current value of IPSR register.
*
* RETURNS: the contents of the IPSR register
* @return the contents of the IPSR register
*
* \NOMANUAL
*/
@ -65,7 +65,7 @@ static ALWAYS_INLINE uint32_t _IpsrGet(void)
*
* Store the value of <msp> in MSP register.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

4
arch/arm/include/CortexM/exc.h
View file

@ -56,7 +56,7 @@ Exception/interrupt context helpers.
* interrupts. Taking a fault within an exception is also considered in
* interrupt context.
*
* RETURNS: 1 if in ISR, 0 if not.
* @return 1 if in ISR, 0 if not.
*
* \NOMANUAL
*/
@ -76,7 +76,7 @@ static ALWAYS_INLINE int _IsInIsr(void)
*
* Enable fault exceptions.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

2
arch/arm/include/CortexM/stack.h
View file

@ -75,7 +75,7 @@ extern char _interrupt_stack[CONFIG_ISR_STACK_SIZE];
* On Cortex-M, the interrupt stack is registered in the MSP (main stack
* pointer) register, and switched to automatically when taking an exception.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

2
arch/arm/include/nano_private.h
View file

@ -192,7 +192,7 @@ static ALWAYS_INLINE void nanoArchInit(void)
* to <value>. It is assumed that the specified <fiber> is pending, and thus
* the fiber's context is stored in its tCCS structure.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

2
arch/arm/ti_lm3s6965/scp.c
View file

@ -53,7 +53,7 @@ volatile struct __scp __scp_section __scp;
*
* _ScpMainOscEnable - enable main oscillator with default frequency of 6MHz
*
* RETURNS: N/A
* @return N/A
*/
void _ScpMainOscEnable(void)
{

6
arch/arm/ti_lm3s6965/system.c
View file

@ -63,7 +63,7 @@ extern void _NmiInit(void);
*
* uart_generic_info_init - initialize generic information for one UART
*
* RETURNS: N/A
* @return N/A
*
*/
@ -85,7 +85,7 @@ inline void uart_generic_info_init(struct uart_init_info *pInfo)
*
* Only used for debugging.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -140,7 +140,7 @@ static void bluetooth_init(void)
* integrated 16550-compatible UART device driver.
* Also initialize the timer device driver, if required.
*
* RETURNS: N/A
* @return N/A
*/
void _InitHardware(void)

2
arch/x86/cache.c
View file

@ -55,7 +55,7 @@ This module contains functions for manipulation caches.
* The cache line size is specified via the CONFIG_CACHE_LINE_SIZE kconfig
* option.
*
* RETURNS: N/A
* @return N/A
*/
void _SysCacheFlush(VIRT_ADDR virt, size_t size)

2
arch/x86/cache_s.S
View file

@ -54,7 +54,7 @@ This module contains functions for manipulating caches.
*
* Both parameters are ignored in this implementation.
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _SysCacheFlush)

24
arch/x86/core/atomic.S
View file

@ -81,7 +81,7 @@ as there is no requirement for this capability.
* and the write of the new value (if it occurs) all happen atomically with
* respect to both interrupts and accesses of other processors to <target>.
*
* RETURNS: Returns 1 if <newValue> is written, 0 otherwise.
* @return Returns 1 if <newValue> is written, 0 otherwise.
*
* int atomic_cas
* (
@ -121,7 +121,7 @@ BRANCH_LABEL(atomic_cas1)
* atomically added to the value at <target>, placing the result at <target>,
* and the old value from <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_add
* (
@ -153,7 +153,7 @@ SECTION_FUNC(TEXT, atomic_add)
* atomically subtracted from the value at <target>, placing the result at
* <target>, and the old value from <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_sub
* (
@ -185,7 +185,7 @@ SECTION_FUNC(TEXT, atomic_sub)
* This routine provides the atomic increment operator. The value at <target>
* is atomically incremented by 1, and the old value from <target> is returned.
*
* RETURNS: The value from <target> before the increment
* @return The value from <target> before the increment
*
* atomic_val_t atomic_inc
* (
@ -217,7 +217,7 @@ SECTION_FUNC(TEXT, atomic_inc)
* This routine provides the atomic decrement operator. The value at <target>
* is atomically decremented by 1, and the old value from <target> is returned.
*
* RETURNS: The value from <target> prior to the decrement
* @return The value from <target> prior to the decrement
*
* atomic_val_t atomic_dec
* (
@ -248,7 +248,7 @@ SECTION_FUNC(TEXT, atomic_dec)
* a value from <target>. It simply does an ordinary load. Note that <target>
* is expected to be aligned to a 4-byte boundary.
*
* RETURNS: The value read from <target>
* @return The value read from <target>
*
* atomic_t atomic_get
* (
@ -271,7 +271,7 @@ SECTION_FUNC(TEXT, atomic_get)
* This routine provides the atomic set operator. The <value> is atomically
* written at <target> and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_set
* (
@ -312,7 +312,7 @@ SECTION_FUNC(TEXT, atomic_set)
* written at <target> and the previous value at <target> is returned. (Hence,
* atomic_clear(pAtomicVar) is equivalent to atomic_set(pAtomicVar, 0).)
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_clear
* (
@ -349,7 +349,7 @@ SECTION_FUNC(TEXT, atomic_clear)
* is atomically bitwise OR'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_or
* (
@ -387,7 +387,7 @@ BRANCH_LABEL(atomic_or_retry)
* is atomically bitwise XOR'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_xor
* (
@ -425,7 +425,7 @@ BRANCH_LABEL(atomic_xor_retry)
* atomically bitwise AND'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_and
* (
@ -463,7 +463,7 @@ BRANCH_LABEL(atomic_and_retry)
* atomically bitwise NAND'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*
* atomic_val_t atomic_nand
* (

24
arch/x86/core/atomic_nolock.c
View file

@ -65,7 +65,7 @@ as there is no requirement for this capability.
* and the write of the new value (if it occurs) all happen atomically with
* respect to both interrupts and accesses of other processors to <target>.
*
* RETURNS: Returns 1 if <newValue> is written, 0 otherwise.
* @return Returns 1 if <newValue> is written, 0 otherwise.
*/
int atomic_cas(
@ -96,7 +96,7 @@ int atomic_cas(
* atomically added to the value at <target>, placing the result at <target>,
* and the old value from <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_add(
@ -122,7 +122,7 @@ atomic_val_t atomic_add(
* atomically subtracted from the value at <target>, placing the result at
* <target>, and the old value from <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_sub(
@ -147,7 +147,7 @@ atomic_val_t atomic_sub(
* This routine provides the atomic increment operator. The value at <target>
* is atomically incremented by 1, and the old value from <target> is returned.
*
* RETURNS: The value from <target> before the increment
* @return The value from <target> before the increment
*/
atomic_val_t atomic_inc(
@ -171,7 +171,7 @@ atomic_val_t atomic_inc(
* This routine provides the atomic decrement operator. The value at <target>
* is atomically decremented by 1, and the old value from <target> is returned.
*
* RETURNS: The value from <target> prior to the decrement
* @return The value from <target> prior to the decrement
*/
atomic_val_t atomic_dec(
@ -196,7 +196,7 @@ atomic_val_t atomic_dec(
* a value from <target>. It simply does an ordinary load. Note that <target>
* is expected to be aligned to a 4-byte boundary.
*
* RETURNS: The value read from <target>
* @return The value read from <target>
*/
atomic_val_t atomic_get(const atomic_t *target /* memory location to read from */
@ -212,7 +212,7 @@ atomic_val_t atomic_get(const atomic_t *target /* memory location to read from *
* This routine provides the atomic set operator. The <value> is atomically
* written at <target> and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_set(
@ -238,7 +238,7 @@ atomic_val_t atomic_set(
* written at <target> and the previous value at <target> is returned. (Hence,
* atomic_clear(pAtomicVar) is equivalent to atomic_set(pAtomicVar, 0).)
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_clear(
@ -263,7 +263,7 @@ atomic_val_t atomic_clear(
* is atomically bitwise OR'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_or(
@ -289,7 +289,7 @@ atomic_val_t atomic_or(
* is atomically bitwise XOR'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_xor(
@ -315,7 +315,7 @@ atomic_val_t atomic_xor(
* atomically bitwise AND'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_and(
@ -341,7 +341,7 @@ atomic_val_t atomic_and(
* atomically bitwise NAND'ed with the value at <target>, placing the result
* at <target>, and the previous value at <target> is returned.
*
* RETURNS: The previous value from <target>
* @return The previous value from <target>
*/
atomic_val_t atomic_nand(

6
arch/x86/core/context.c
View file

@ -67,7 +67,7 @@ void _ContextEntryWrapper(_ContextEntry, _ContextArg, _ContextArg, _ContextArg);
*
* This function is called by _NewContext() to initialize task contexts.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -260,7 +260,7 @@ static void _NewContextInternal(
* first time that the new context is swapped in, and it jumps to
* _context_entry after it has done its work.
*
* RETURNS: this routine does NOT return.
* @return this routine does NOT return.
*
* \NOMANUAL
*/
@ -283,7 +283,7 @@ __asm__("\t.globl _context_entry\n"
* The "context control block" (CCS) is carved from the "end" of the specified
* context stack memory.
*
* RETURNS: opaque pointer to initialized CCS structure
* @return opaque pointer to initialized CCS structure
*
* \NOMANUAL
*/

4
arch/x86/core/cpuhalt.S
View file

@ -73,7 +73,7 @@ by nano_cpu_atomic_idle().
* '_sys_power_save_flag' variable is non-zero. The IA-32 'hlt' instruction
* will be issued causing a low-power consumption sleep mode.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*
@ -113,7 +113,7 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
* 2) After waking up from the low-power mode, the interrupt lockout state
* must be restored as indicated in the 'imask' input parameter.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*

4
arch/x86/core/excconnect.c
View file

@ -110,7 +110,7 @@ void _NanoCpuExcConnectAtDpl(unsigned int vector,
* The handler is connected via an interrupt-gate descriptor having a
* descriptor privilege level (DPL) equal to zero.
*
* RETURNS: N/A
* @return N/A
*
* INTERNAL
* The function prototype for nanoCpuExcConnect() only exists in nano_private.h,
@ -150,7 +150,7 @@ void nanoCpuExcConnect(unsigned int vector, /* interrupt vector: 0 to 255 on
* The handler is connected via an interrupt-gate descriptor having the supplied
* descriptor privilege level (DPL).
*
* RETURNS: N/A
* @return N/A
*
* INTERNAL
* The function prototype for nanoCpuExcConnect() only exists in nano_private.h,

4
arch/x86/core/excstub.S
View file

@ -75,7 +75,7 @@ and exiting a C exception handler.
* created by this routine to determine the locations of volatile registers.
* These tools must be updated to reflect any changes to the stack frame.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*
@ -224,7 +224,7 @@ BRANCH_LABEL(allDone)
* completed. This routine restores the volatile integer registers and
* then control is returned back to the interrupted context or ISR.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*

2
arch/x86/core/fatal.c
View file

@ -76,7 +76,7 @@ const NANO_ESF _default_esf = {
* fatal error does not have a hardware generated ESF, the caller should either
* create its own or use a pointer to the global default ESF <_default_esf>.
*
* RETURNS: This function does not return.
* @return This function does not return.
*
* \NOMANUAL
*/

4
arch/x86/core/ffs.S
View file

@ -60,7 +60,7 @@ are defined in arch.h.
* at 1 from the least significant bit to 32 for the most significant bit.
* A return value of zero indicates that the value passed is zero.
*
* RETURNS: bit position from 1 to 32, or 0 if the argument is zero.
* @return bit position from 1 to 32, or 0 if the argument is zero.
*
* INTERNAL
* For Intel64 (x86_64) architectures, the 'cmovz' can be removed
@ -103,7 +103,7 @@ BRANCH_LABEL(ffsLsb_argNotZero) /* this label serves find_first_set() & find_las
* at 1 from the least significant bit to 32 for the most significant bit.
* A return value of zero indicates that the value passed is zero.
*
* RETURNS: bit position from 1 to 32, or 0 if the argument is zero.
* @return bit position from 1 to 32, or 0 if the argument is zero.
*
* INTERNAL
* For Intel64 (x86_64) architectures, the 'cmovz' can be removed

18
arch/x86/core/float.c
View file

@ -120,7 +120,7 @@ extern uint32_t _sse_mxcsr_default_value; /* SSE control/status register default
* specified CCS. If the specified task or fiber supports SSE then
* x87/MMX/SSEx context info is saved, otherwise only x87/MMX context is saved.
*
* RETURNS: N/A
* @return N/A
*/
static void _FpCtxSave(tCCS *ccs)
@ -134,7 +134,7 @@ static void _FpCtxSave(tCCS *ccs)
*
* This routine initializes the system's "live" non-integer context.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _FpCtxInit(tCCS *ccs)
@ -163,7 +163,7 @@ static inline void _FpCtxInit(tCCS *ccs)
* This routine should only be used to enable floating point support for a
* task/fiber that does not currently have such support enabled already.
*
* RETURNS: N/A
* @return N/A
*
* INTERNAL
* Since the transition from "non-FP supporting" to "FP supporting" must be done
@ -296,7 +296,7 @@ void _FpEnable(tCCS *ccs,
*
* See the description of _FpEnable() for further details.
*
* RETURNS: N/A
* @return N/A
*/
FUNC_ALIAS(_FpEnable, fiber_float_enable, void);
@ -310,7 +310,7 @@ FUNC_ALIAS(_FpEnable, fiber_float_enable, void);
*
* See the description of _FpEnable() for further details.
*
* RETURNS: N/A
* @return N/A
*/
FUNC_ALIAS(_FpEnable, task_float_enable, void);
@ -327,7 +327,7 @@ FUNC_ALIAS(_FpEnable, task_float_enable, void);
* This routine should only be used to disable floating point support for
* a task/fiber that currently has such support enabled.
*
* RETURNS: N/A
* @return N/A
*
* INTERNAL
* Since the transition from "FP supporting" to "non-FP supporting" must be done
@ -389,7 +389,7 @@ void _FpDisable(tCCS *ccs)
* This routine should only be used to disable floating point support for
* a task/fiber that currently has such support enabled.
*
* RETURNS: N/A
* @return N/A
*/
FUNC_ALIAS(_FpDisable, fiber_float_disable, void);
@ -406,7 +406,7 @@ FUNC_ALIAS(_FpDisable, fiber_float_disable, void);
* This routine should only be used to disable floating point support for
* a task/fiber that currently has such support enabled.
*
* RETURNS: N/A
* @return N/A
*/
FUNC_ALIAS(_FpDisable, task_float_disable, void);
@ -426,7 +426,7 @@ FUNC_ALIAS(_FpDisable, task_float_disable, void);
* current task or fiber with the USE_FP option (or the USE_SSE option if the
* SSE configuration option has been enabled).
*
* RETURNS: N/A
* @return N/A
*/
void _FpNotAvailableExcHandler(NANO_ESF * pEsf /* not used */

10
arch/x86/core/intconnect.c
View file

@ -162,7 +162,7 @@ static NANO_INT_STUB dynamic_stubs[ALL_DYNAMIC_STUBS] = {
/**
* _int_stub_alloc - allocate dynamic interrupt stub
*
* RETURNS: index of the first available element of the STUB array or -1
* @return index of the first available element of the STUB array or -1
* if all elements are used
*/
static int _int_stub_alloc(void)
@ -192,7 +192,7 @@ static int _int_stub_alloc(void)
* and exceptions should specify a level of 0, whereas handlers for user-mode
* software generated interrupts should specify 3.
*
* RETURNS: N/A
* @return N/A
*
* INTERNAL
* Unlike nanoCpuExcConnect() and irq_connect(), the _IntVecSet() routine
@ -260,7 +260,7 @@ void _IntVecSet(
* The routine searches for the first available element in the synamic_stubs
* array and uses it for the stub.
*
* RETURNS: the allocated interrupt vector
* @return the allocated interrupt vector
*
* WARNINGS
* Some boards utilize interrupt controllers where the interrupt vector
@ -502,7 +502,7 @@ int irq_connect(
* For example, the local APIC on Pentium4 and later processors, the in-service
* register (ISR) and the interrupt request register (IRR) are 256 bits wide.
*
* RETURNS: allocated interrupt vector
* @return allocated interrupt vector
*
* INTERNAL
* For debug kernels, this routine shall return -1 when there are no
@ -610,7 +610,7 @@ int _IntVecAlloc(unsigned int priority)
* as allocated so that any future invocations of _IntVecAllocate() will not
* return that vector.
*
* RETURNS: N/A
* @return N/A
*
*/

2
arch/x86/core/inthndlset.c
View file

@ -76,7 +76,7 @@ extern unsigned char _idt_base_address[];
* and/or parameter. If possible, silence the source of the associated interrupt
* only, rather than locking out all interrupts.
*
* RETURNS: N/A
* @return N/A
*
*/

8
arch/x86/core/intstub.S
View file

@ -101,7 +101,7 @@ entering and exiting a C interrupt handler.
* created by this routine to determine the locations of volatile registers.
* These tools must be updated to reflect any changes to the stack frame.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*
@ -255,7 +255,7 @@ BRANCH_LABEL(_HandleIdle)
* in which case one or more other fiber and task contexts will execute before
* this routine resumes and control gets returned to the interrupted task.
*
* RETURNS: N/A
* @return N/A
*
* C function prototype:
*
@ -405,7 +405,7 @@ BRANCH_LABEL(nestedInterrupt)
* to return to the interrupted context and thus the volatile registers
* are not saved.
*
* RETURNS: Never returns
* @return Never returns
*
* C function prototype:
*
@ -487,7 +487,7 @@ BRANCH_LABEL(callFatalHandler)
* to block, the interrupt disable state will be restored when the context is
* later rescheduled for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* @return An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*/

4
arch/x86/core/msr.S
View file

@ -65,7 +65,7 @@ utilities.
* 2) The 'wrmsr' uses the ECX, EDX, and EAX registers which matches the set of
* volatile registers!
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _MsrWrite)
@ -96,7 +96,7 @@ SECTION_FUNC(TEXT, _MsrWrite)
* 2) The 'rdmsr' uses the ECX, EDX, and EAX registers which matches the set of
* volatile registers!
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _MsrRead)

2
arch/x86/core/swap.S
View file

@ -99,7 +99,7 @@ save frame on the stack.
* no runnable FIBER contexts, then schedule the TASK context represented
* by _nanokernel.task. The _nanokernel.task field will never be NULL.
*
* RETURNS: may contain a return value setup by a call to fiberRtnValueSet()
* @return may contain a return value setup by a call to fiberRtnValueSet()
*
* C function prototype:
*

6
arch/x86/generic_pc/system.c
View file

@ -90,7 +90,7 @@ static inline void ioapicInit(void)
*
* uart_generic_info_init - initialize initialization information for one UART
*
* RETURNS: N/A
* @return N/A
*
*/
@ -112,7 +112,7 @@ void uart_generic_info_init(struct uart_init_info *p_info)
*
* Only used for debugging.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -157,7 +157,7 @@ static void bluetooth_init(void)
* Intel 8250 UART device driver.
* Also initialize the timer device driver, if required.
*
* RETURNS: N/A
* @return N/A
*/
void _InitHardware(void)

6
arch/x86/include/advidle.h
View file

@ -48,7 +48,7 @@ and _AdvIdleStart() functions.
* This routine checks if the system is recovering from advanced
* sleep or cold booting.
*
* RETURNS: 0 if the system is cold booting on a non-zero
* @return 0 if the system is cold booting on a non-zero
* value if the system is recovering from advanced sleep.
*/
@ -63,7 +63,7 @@ extern int _AdvIdleCheckSleep(void);
* passes to the _AdvIdleFunc() that put the system to sleep, which then
* finishes executing.
*
* RETURNS: does not return to caller
* @return does not return to caller
*/
extern void _AdvIdleStart(
@ -80,7 +80,7 @@ extern void _AdvIdleStart(
* to sleep and then later allows it to resume processing; if not, the routine
* returns immediately without sleeping.
*
* RETURNS: non-zero if advanced sleep occurred; otherwise zero
* @return non-zero if advanced sleep occurred; otherwise zero
*/
extern int _AdvIdleFunc(int32_t ticks /* upcoming kernel idle time */

8
arch/x86/include/asm_inline_gcc.h
View file

@ -49,7 +49,7 @@ NANO_CPU_EXC_CONNECT_NO_ERR(handler,vector,0)
*
* EflagsGet - return the current value of the EFLAGS register
*
* RETURNS: the EFLAGS register.
* @return the EFLAGS register.
*
* \NOMANUAL
*/
@ -77,7 +77,7 @@ static inline unsigned int EflagsGet(void)
* This routine sets CR0[TS] to 1, which disallows the use of FP instructions
* by the currently executing context.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _FpAccessDisable(void)
@ -103,7 +103,7 @@ static inline void _FpAccessDisable(void)
* x87/MMX/SSEx context info is saved, otherwise only x87/MMX context is saved.
* Function is invoked by _FpCtxSave(tCCS *ccs)
*
* RETURNS: N/A
* @return N/A
*/
static inline void _do_fp_ctx_save(int flags, void *preemp_float_reg)
@ -133,7 +133,7 @@ static inline void _do_fp_ctx_save(int flags, void *preemp_float_reg)
* This routine initializes the system's "live" non-integer context.
* Function is invoked by _FpCtxInit(tCCS *ccs)
*
* RETURNS: N/A
* @return N/A
*/
static inline void _do_fp_ctx_init(int flags)

4
arch/x86/include/nano_private.h
View file

@ -768,7 +768,7 @@ extern tNANO _nanokernel;
* Trivial stuff is done inline; more complex initialization is done via
* function calls.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -817,7 +817,7 @@ static inline void nanoArchInit(void)
* set to <value>. It is assumed that the specified <fiber> is pending, and
* thus the fibers context is stored in its tCCS structure.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

16
arch/x86/quark/board.h
View file

@ -156,7 +156,7 @@ the 'Quark' BSP.
*
* outByte - output byte to memory location
*
* RETURNS: N/A
* @return N/A
*
* NOMANUAL
*/
@ -173,7 +173,7 @@ static inline void outByte(uint8_t data, uint32_t addr)
* This function issues the 'move' instruction to read a byte from the specified
* memory address.
*
* RETURNS: the byte read from the specified memory address
* @return the byte read from the specified memory address
*
* NOMANUAL
*/
@ -198,7 +198,7 @@ static inline uint8_t inByte(uint32_t addr)
*
* outWord - output word to memory location
*
* RETURNS: N/A
* @return N/A
*
* NOMANUAL
*/
@ -215,7 +215,7 @@ static inline void outWord(uint16_t data, uint32_t addr)
* This function issues the 'move' instruction to read a word from the specified
* memory address.
*
* RETURNS: the word read from the specified memory address
* @return the word read from the specified memory address
*
* NOMANUAL
*/
@ -240,7 +240,7 @@ static inline uint16_t inWord(uint32_t addr)
*
* outLong - output long word to memory location
*
* RETURNS: N/A
* @return N/A
*
* NOMANUAL
*/
@ -257,7 +257,7 @@ static inline void outLong(uint32_t data, uint32_t addr)
* This function issues the 'move' instruction to read a word from the specified
* memory address.
*
* RETURNS: the long word read from the specified memory address
* @return the long word read from the specified memory address
*
* NOMANUAL
*/
@ -278,7 +278,7 @@ static inline uint32_t inLong(uint32_t addr)
* INTC (pin 3) -> IRQ 18
* INTD (pin 4) -> IRQ 19
*
* RETURNS: IRQ number, -1 if the result is incorrect
* @return IRQ number, -1 if the result is incorrect
*
*/
@ -293,7 +293,7 @@ static inline int pci_pin2irq(int pin)
*
* pci_irq2pin - convert IRQ to PCI interrupt pin
*
* RETURNS: pin number, -1 if the result is incorrect
* @return pin number, -1 if the result is incorrect
*
*/

6
arch/x86/quark/system.c
View file

@ -59,7 +59,7 @@ Handlers for the secondary serial port have not been added.
*
* uart_generic_info_init - initialize initialization information for one UART
*
* RETURNS: N/A
* @return N/A
*
*/
@ -80,7 +80,7 @@ void uart_generic_info_init(struct uart_init_info *p_info)
*
* Only used for debugging.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -109,7 +109,7 @@ static void consoleInit(void)
* Intel 8250 UART device driver.
* Also initialize the timer device driver, if required.
*
* RETURNS: N/A
* @return N/A
*/
void _InitHardware(void)

2
arch/x86/sys_fatal_error_handler.c
View file

@ -62,7 +62,7 @@ supported BSPs.
* implementation to take other actions, such as logging error (or debug)
* information to a persistent repository and/or rebooting the system.
*
* RETURNS: This function does not return.
* @return This function does not return.
*
* \NOMANUAL
*/

2
arch/x86/task/strtask.c
View file

@ -55,7 +55,7 @@ Intel-specific parts of start_task(). Only FP functionality currently.
*
* _StartTaskArch - Intel-specifc parts of task initialization
*
* RETURNS: N/A
* @return N/A
*/
void _StartTaskArch(

6
drivers/console/uart_console.c
View file

@ -60,7 +60,7 @@
*
* consoleIn - get a character from UART
*
* RETURNS: the character or EOF if nothing present
* @return the character or EOF if nothing present
*/
static int consoleIn(void)
@ -80,7 +80,7 @@ static int consoleIn(void)
*
* Outputs both line feed and carriage return in the case of a '\n'.
*
* RETURNS: The character passed as input.
* @return The character passed as input.
*/
static int consoleOut(int c /* character to output */
@ -213,7 +213,7 @@ void uart_register_input(struct nano_fifo *avail, struct nano_fifo *lines)
*
* uart_console_init - initialize one UART as the console/debug port
*
* RETURNS: N/A
* @return N/A
*/
void uart_console_init(void)

6
drivers/interrupt_controller/arcv2_irq_unit.c
View file

@ -53,7 +53,7 @@
* the window between a write to IRQ_SELECT and subsequent writes to the
* selected IRQ's registers.
*
* RETURNS: N/A
* @return N/A
*/
void _arc_v2_irq_unit_init(void)
@ -77,7 +77,7 @@ void _arc_v2_irq_unit_init(void)
* Interrupts must be locked or the ISR operating at P0 when invoking this
* function.
*
* RETURNS: N/A
* @return N/A
*/
void _arc_v2_irq_unit_int_eoi(int irq)
@ -93,7 +93,7 @@ void _arc_v2_irq_unit_int_eoi(int irq)
* edge of the signal. Valid values for <trigger> are _ARC_V2_INT_LEVEL and
* _ARC_V2_INT_PULSE.
*
* RETURNS: N/A
* @return N/A
*/
void _arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger)

12
drivers/interrupt_controller/i8259.c
View file

@ -123,7 +123,7 @@ FUNC_ALIAS(_i8259_irq_disable, irq_disable, void);
* This routine initializes the Intel 8259A PIC device driver and the device
* itself.
*
* RETURNS: N/A
* @return N/A
*/
void _i8259_init(void)
@ -191,7 +191,7 @@ void _i8259_init(void)
*
* This routine is called at the end of the interrupt handler.
*
* RETURNS: N/A
* @return N/A
*
* ERRNO
*/
@ -214,7 +214,7 @@ void _i8259_eoi_master(unsigned int irq /* IRQ number to
* This routine is called at the end of the interrupt handler in the Normal
* Fully Nested Mode.
*
* RETURNS: N/A
* @return N/A
*
* ERRNO
*/
@ -251,7 +251,7 @@ void _i8259_eoi_slave(unsigned int irq /* IRQ number to
* This function is called by _i8259_irq_enable() and _i8259_irq_disable() to
* perform the actual enabling/disabling of an IRQ to minimize footprint.
*
* RETURNS: N/A
* @return N/A
*
* see also: _i8259_irq_disable()/_i8259_irq_enable
*/
@ -296,7 +296,7 @@ static void __I8259IntEnable(
*
* This routine disables a specified PIC interrupt input line.
*
* RETURNS: N/A
* @return N/A
*
* SEE ALSO: _i8259_irq_enable()
*/
@ -313,7 +313,7 @@ void _i8259_irq_disable(unsigned int irq /* IRQ number to disable */
*
* This routine enables a specified PIC interrupt input line.
*
* RETURNS: N/A
* @return N/A
*
* SEE ALSO: _i8259_irq_disable()
*/

4
drivers/interrupt_controller/i8259_boi.S
View file

@ -71,7 +71,7 @@ a real IRQ has been inserted.
*
* void _i8259_boi_master (void)
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _i8259_boi_master)
@ -105,7 +105,7 @@ SECTION_FUNC(TEXT, _i8259_boi_master)
*
* void _i8259_boi_slave (void)
*
* RETURNS: N/A
* @return N/A
*/
SECTION_FUNC(TEXT, _i8259_boi_slave)

30
drivers/interrupt_controller/ioapic_intr.c
View file

@ -215,7 +215,7 @@ static void _IoApicRedUpdateLo(unsigned int irq, uint32_t value,
*
* This routine initializes the IO APIC or xAPIC.
*
* RETURNS: N/A
* @return N/A
*/
void _ioapic_init(void)
@ -267,7 +267,7 @@ void _ioapic_init(void)
*
* This routine sends an EOI signal to the IO APIC's interrupting source.
*
* RETURNS: N/A
* @return N/A
*/
void _ioapic_eoi(unsigned int irq /* INT number to send EOI */
@ -283,7 +283,7 @@ void _ioapic_eoi(unsigned int irq /* INT number to send EOI */
*
* This routine returns EOI signalling information for a specific IRQ.
*
* RETURNS: address of routine to be called to signal EOI;
* @return address of routine to be called to signal EOI;
* as a side effect, also passes back indication if routine requires
* an interrupt vector argument and what the argument value should be
*/
@ -323,7 +323,7 @@ void *_ioapic_eoi_get(unsigned int irq, /* INTIN number of interest */
*
* This routine enables a specified APIC interrupt input line.
*
* RETURNS: N/A
* @return N/A
*/
void _ioapic_irq_enable(unsigned int irq /* INTIN number to enable */
@ -338,7 +338,7 @@ void _ioapic_irq_enable(unsigned int irq /* INTIN number to enable */
*
* This routine disables a specified APIC interrupt input line.
*
* RETURNS: N/A
* @return N/A
*/
void _ioapic_irq_disable(unsigned int irq /* INTIN number to disable */
@ -353,7 +353,7 @@ void _ioapic_irq_disable(unsigned int irq /* INTIN number to disable */
*
* This routine sets up the redirection table entry for the specified IRQ
*
* RETURNS: N/A
* @return N/A
*/
void _ioapic_irq_set(unsigned int irq, /* virtualized IRQ */
unsigned int vector, /* vector number */
@ -375,7 +375,7 @@ void _ioapic_irq_set(unsigned int irq, /* virtualized IRQ */
* The routine writes the interrupt vector in the Interrupt Redirection
* Table for specified irq number
*
* RETURNS: N/A
* @return N/A
*/
void _ioapic_int_vec_set(unsigned int irq, /* INT number */
unsigned int vector /* vector number */
@ -392,7 +392,7 @@ void _ioapic_int_vec_set(unsigned int irq, /* INT number */
*
* This routine reads the specified IO APIC register using indirect addressing.
*
* RETURNS: register value
* @return register value
*/
static uint32_t __IoApicGet(
@ -420,7 +420,7 @@ static uint32_t __IoApicGet(
*
* This routine writes the specified IO APIC register using indirect addressing.
*
* RETURNS: N/A
* @return N/A
*/
static void __IoApicSet(
@ -448,7 +448,7 @@ static void __IoApicSet(
*
* This routine reads the low-order 32 bits of a Redirection Table entry.
*
* RETURNS: 32 low-order bits
* @return 32 low-order bits
*/
static uint32_t ioApicRedGetLo(unsigned int irq /* INTIN number */
@ -474,7 +474,7 @@ static uint32_t ioApicRedGetLo(unsigned int irq /* INTIN number */
*
* This routine writes the low-order 32 bits of a Redirection Table entry.
*
* RETURNS: N/A
* @return N/A
*/
static void ioApicRedSetLo(unsigned int irq, /* INTIN number */
@ -501,7 +501,7 @@ static void ioApicRedSetLo(unsigned int irq, /* INTIN number */
*
* This routine writes the high-order 32 bits of a Redirection Table entry.
*
* RETURNS: N/A
* @return N/A
*/
static void ioApicRedSetHi(unsigned int irq, /* INTIN number */
@ -529,7 +529,7 @@ static void ioApicRedSetHi(unsigned int irq, /* INTIN number */
* This routine modifies selected portions of the low-order 32 bits of a
* Redirection Table entry, as indicated by the associate bit mask.
*
* RETURNS: N/A
* @return N/A
*/
static void _IoApicRedUpdateLo(
@ -555,7 +555,7 @@ static void _IoApicRedUpdateLo(
* This routine writes the specified 32-bit <value> into the RTE configuration
* register for the specified <irq> (0 to (IOAPIC_NUM_RTES - 1))
*
* RETURNS: void
* @return void
*/
static void _IoApicRteConfigSet(unsigned int irq, /* INTIN number */
@ -583,7 +583,7 @@ static void _IoApicRteConfigSet(unsigned int irq, /* INTIN number */
* This routine writes the 32-bit <value> into the redirection register
* specified by <reg>.
*
* RETURNS: void
* @return void
*/
static void _IoApicRedirRegSet(unsigned int reg, uint32_t value)

14
drivers/interrupt_controller/loapic_intr.c
View file

@ -204,7 +204,7 @@ INCLUDE FILES: loapic.h
*
* This routine initializes Local APIC or xAPIC.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -266,7 +266,7 @@ void _loapic_init(void)
*
* This routine enables the Local xAPIC.
*
* RETURNS: N/A
* @return N/A
*/
void _loapic_enable(void)
@ -284,7 +284,7 @@ void _loapic_enable(void)
*
* This routine disables the Local xAPIC.
*
* RETURNS: N/A
* @return N/A
*/
void _loapic_disable(void)
@ -302,7 +302,7 @@ void _loapic_disable(void)
*
* This routine sends an EOI signal to the Local APIC's interrupting source.
*
* RETURNS: N/A
* @return N/A
*/
void _loapic_eoi(unsigned int irq)
@ -320,7 +320,7 @@ void _loapic_eoi(unsigned int irq)
* a vector has been allocated, this routine is invoked to update the LVT
* entry associated with <irq> with the vector.
*
* RETURNS: N/A
* @return N/A
*/
void _loapic_int_vec_set(unsigned int irq, /* IRQ number of the
@ -360,7 +360,7 @@ void _loapic_int_vec_set(unsigned int irq, /* IRQ number of the
*
* This routine clears the interrupt mask bit in the LVT for the specified IRQ
*
* RETURNS: N/A
* @return N/A
*/
void _loapic_irq_enable(unsigned int irq /* IRQ number of
@ -390,7 +390,7 @@ void _loapic_irq_enable(unsigned int irq /* IRQ number of
*
* This routine clears the interrupt mask bit in the LVT for the specified IRQ
*
* RETURNS: N/A
* @return N/A
*/
void _loapic_irq_disable(unsigned int irq /* IRQ number of the

6
drivers/interrupt_controller/system_apic.c
View file

@ -81,7 +81,7 @@ for the atom_n28xx variant of generic_pc BSP.
* The IOAPIC_NUM_RTES macro is provided by board.h, and it specifies the number
* of IRQs supported by the on-board I/O APIC device.
*
* RETURNS: the allocated interrupt vector
* @return the allocated interrupt vector
*
* INTERNAL
* For debug kernels, this routine will return -1 if there are no vectors
@ -219,7 +219,7 @@ void _SysIntVecProgram(unsigned int vector, /* vector number */
* IRQ virtualization that is performed by this BSP. See the comments
* in _SysIntVecAlloc() for more information regarding IRQ virtualization.
*
* RETURNS: N/A
* @return N/A
*/
void irq_enable(unsigned int irq)
@ -239,7 +239,7 @@ void irq_enable(unsigned int irq)
* IRQ virtualization that is performed by this BSP. See the comments
* in _SysIntVecAlloc() for more information regarding IRQ virtualization.
*
* RETURNS: N/A
* @return N/A
*/
void irq_disable(unsigned int irq)

2
drivers/interrupt_controller/system_pic.c
View file

@ -67,7 +67,7 @@ IRQ_CONNECT_STATIC(pic_slave, PIC_SLAVE_STRAY_INT_LVL, 0, _i8259_boi_slave, 0);
* - IRQ0 to IRQ7 are provided by the master i8259 PIC
* - IRQ8 to IRQ15 are provided by the slave i8259 PIC
*
* RETURNS: the allocated interrupt vector
* @return the allocated interrupt vector
*
* INTERNAL
* For debug kernels, this routine will return -1 for invalid <priority> or

10
drivers/pci/pci.c
View file

@ -171,7 +171,7 @@ static struct lookup_data __noinit lookup;
*
* pci_get_bar_config - return the configuration for the specified BAR
*
* RETURNS: 0 if BAR is implemented, -1 if not.
* @return 0 if BAR is implemented, -1 if not.
*/
static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
@ -216,7 +216,7 @@ static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
*
* pci_bar_params_get - retrieve the I/O address and IRQ of the specified BAR
*
* RETURNS: -1 on error, 0 if 32 bit BAR retrieved or 1 if 64 bit BAR retrieved
* @return -1 on error, 0 if 32 bit BAR retrieved or 1 if 64 bit BAR retrieved
*
* NOTE: Routine does not set up parameters for 64 bit BARS, they are ignored.
*
@ -267,7 +267,7 @@ static inline int pci_bar_params_get(union pci_addr_reg pci_ctrl_addr,
*
* pci_dev_scan - scan the specified PCI device for all sub functions
*
* RETURNS: 1 if a device has been found, 0 otherwise.
* @return 1 if a device has been found, 0 otherwise.
*
* \NOMANUAL
*/
@ -382,7 +382,7 @@ void pci_bus_scan_init(void)
* given dev_info at first call. Which criterias can be class and/or
* vendor_id/device_id.
*
* RETURNS: 1 on success, 0 otherwise. On success, dev_info is filled in with
* @return 1 on success, 0 otherwise. On success, dev_info is filled in with
* currently found device information
*
* \NOMANUAL
@ -434,7 +434,7 @@ int pci_bus_scan(struct pci_dev_info *dev_info)
*
* Shows the PCI device found provided as parameter.
*
* RETURNS: N/A
* @return N/A
*/
void pci_show(struct pci_dev_info *dev_info)

14
drivers/pci/pci_config.c
View file

@ -62,7 +62,7 @@ This module implements the PCI config space access functions
* @param offset Offset into the configuration space.
* @param data Data written to the offset.
*
* RETURNS: N/A
* @return N/A
*/
void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint32_t data)
@ -92,7 +92,7 @@ void pci_config_out_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
* @param offset Offset into the configuration space.
* @param data Data written to the offset.
*
* RETURNS: N/A
* @return N/A
*/
void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint16_t data)
@ -122,7 +122,7 @@ void pci_config_out_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
* @param offset Offset into the configuration space.
* @param data Data written to the offset.
*
* RETURNS: N/A
* @return N/A
*/
void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
uint32_t offset, uint8_t data)
@ -152,7 +152,7 @@ void pci_config_out_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
* @param offset Offset into the configuration space.
* @param data Data read from the offset.
*
* RETURNS: N/A
* @return N/A
*
*/
void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
@ -183,7 +183,7 @@ void pci_config_in_long(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
* @param offset Offset into the configuration space.
* @param data Data read from the offset.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -220,7 +220,7 @@ void pci_config_in_word(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
* @param offset Offset into the configuration space.
* @param data Data read from the offset.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -261,7 +261,7 @@ void pci_config_in_byte(uint32_t bus_no, uint32_t device_no, uint32_t func_no,
* @param function PCI function number.
* @param p_offset Returned config space offset.
*
* RETURNS: 0 if Extended Capability found, -1 otherwise
* @return 0 if Extended Capability found, -1 otherwise
*
*/

16
drivers/pci/pci_interface.c
View file

@ -59,7 +59,7 @@ This module implements the PCI H/W access functions.
* This routine reads the specified register from the PCI controller and
* places the data into the provided buffer.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -93,7 +93,7 @@ static void pci_ctrl_read(uint32_t reg, /* PCI register to read */
* This routine writes the provided data to the specified register in the PCI
* controller.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -127,7 +127,7 @@ static void pci_ctrl_write(uint32_t reg, /* PCI register to write */
*
* This routine reads the data register of the specified PCI controller.
*
* RETURNS: 0 or -1
* @return 0 or -1
*
*/
@ -154,7 +154,7 @@ static int pci_ctrl_data_read(uint32_t controller, /* controller number */
* This routine writes the provided data to the data register of the
* specified PCI controller.
*
* RETURNS: 0 or -1
* @return 0 or -1
*
*/
@ -181,7 +181,7 @@ static int pci_ctrl_data_write(uint32_t controller, /* controller number */
* This routine writes the provided data to the address register of the
* specified PCI controller.
*
* RETURNS: 0 or -1
* @return 0 or -1
*
*/
@ -243,7 +243,7 @@ static int pci_ctrl_addr_write(uint32_t controller, /* controller number */
* Reading of PCI data must be performed as an atomic operation. It is up to
* the caller to enforce this.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -333,7 +333,7 @@ void pci_read(uint32_t controller, /* PCI controller to use */
* the caller to enforce this.
*
*
* RETURNS: N/A
* @return N/A
*
*/
@ -386,7 +386,7 @@ void pci_write(uint32_t controller, /* controller to use */
* This routine reads the PCI header for the specified device and puts the
* result in the supplied header structure.
*
* RETURNS: N/A
* @return N/A
*/
void pci_header_get(uint32_t controller,

4
drivers/random/rand32-timer.c
View file

@ -61,7 +61,7 @@ static atomic_val_t _rand32_counter = 0;
* This routine is automatically invoked by the kernel during system
* initialization.
*
* RETURNS: N/A
* @return N/A
*/
@ -77,7 +77,7 @@ void sys_rand32_init(void)
* target's clock counter, which means that successive calls will return
* different values.
*
* RETURNS: a 32-bit number
* @return a 32-bit number
*/
uint32_t sys_rand32_get(void)

4
drivers/random/rand32-timestamp.c
View file

@ -49,7 +49,7 @@ number generator.
* The non-random number generator does not require any initialization.
* Routine is automatically invoked by the kernel during system startup.
*
* RETURNS: N/A
* @return N/A
*/
void sys_rand32_init(void)
@ -64,7 +64,7 @@ void sys_rand32_init(void)
* CPU's timestamp counter, which means that successive calls will normally
* display ever-increasing values.
*
* RETURNS: a 32-bit number
* @return a 32-bit number
*/
uint32_t sys_rand32_get(void)

32
drivers/serial/k20UartDrv.c
View file

@ -66,7 +66,7 @@ UART_PORTS_CONFIGURE(_k20Uart_t, uart);
* This routine is called to reset the chip in a quiescent state.
* It is assumed that this function is called only once per UART.
*
* RETURNS: N/A
* @return N/A
*/
void uart_init(int port, /* UART channel to initialize */
@ -111,7 +111,7 @@ void uart_init(int port, /* UART channel to initialize */
*
* uart_poll_in - poll the device for input.
*
* RETURNS: 0 if a character arrived, -1 if the input buffer if empty.
* @return 0 if a character arrived, -1 if the input buffer if empty.
*/
int uart_poll_in(int port, /* UART channel to select for input */
@ -139,7 +139,7 @@ int uart_poll_in(int port, /* UART channel to select for input */
* If the hardware flow control is enabled then the handshake signal CTS has to
* be asserted in order to send a character.
*
* RETURNS: sent character
* @return sent character
*/
unsigned char uart_poll_out(
int port, /* UART channel to select for output */
@ -163,7 +163,7 @@ unsigned char uart_poll_out(
*
* uart_fifo_fill - fill FIFO with data
* RETURNS: number of bytes sent
* @return number of bytes sent
*/
int uart_fifo_fill(int port, /* UART on port to send */
@ -185,7 +185,7 @@ int uart_fifo_fill(int port, /* UART on port to send */
*
* uart_fifo_read - read data from FIFO
*
* RETURNS: number of bytes read
* @return number of bytes read
*/
int uart_fifo_read(int port, /* UART to receive from */
@ -207,7 +207,7 @@ int uart_fifo_read(int port, /* UART to receive from */
*
* uart_irq_tx_enable - enable TX interrupt
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_tx_enable(int port /* UART to enable Tx
@ -223,7 +223,7 @@ void uart_irq_tx_enable(int port /* UART to enable Tx
*
* uart_irq_tx_disable - disable TX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_tx_disable(
@ -239,7 +239,7 @@ void uart_irq_tx_disable(
*
* uart_irq_tx_ready - check if Tx IRQ has been raised
*
* RETURNS: 1 if an IRQ is ready, 0 otherwise
* @return 1 if an IRQ is ready, 0 otherwise
*/
int uart_irq_tx_ready(int port /* UART to check */
@ -254,7 +254,7 @@ int uart_irq_tx_ready(int port /* UART to check */
*
* uart_irq_rx_enable - enable RX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_rx_enable(int port /* UART to enable Rx
@ -270,7 +270,7 @@ void uart_irq_rx_enable(int port /* UART to enable Rx
*
* uart_irq_rx_disable - disable RX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_rx_disable(
@ -286,7 +286,7 @@ void uart_irq_rx_disable(
*
* uart_irq_rx_ready - check if Rx IRQ has been raised
*
* RETURNS: 1 if an IRQ is ready, 0 otherwise
* @return 1 if an IRQ is ready, 0 otherwise
*/
int uart_irq_rx_ready(int port /* UART to check */
@ -301,7 +301,7 @@ int uart_irq_rx_ready(int port /* UART to check */
*
* uart_irq_err_enable - enable error interrupt
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_err_enable(int port)
@ -320,7 +320,7 @@ void uart_irq_err_enable(int port)
*
* uart_irq_err_disable - disable error interrupt
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_err_disable(int port /* UART to disable Rx interrupt */
@ -340,7 +340,7 @@ void uart_irq_err_disable(int port /* UART to disable Rx interrupt */
*
* uart_irq_is_pending - check if Tx or Rx IRQ is pending
*
* RETURNS: 1 if a Tx or Rx IRQ is pending, 0 otherwise
* @return 1 if a Tx or Rx IRQ is pending, 0 otherwise
*/
int uart_irq_is_pending(int port /* UART to check */
@ -359,7 +359,7 @@ int uart_irq_is_pending(int port /* UART to check */
*
* uart_irq_update - update IRQ status
*
* RETURNS: always 1
* @return always 1
*/
int uart_irq_update(int port)
@ -373,7 +373,7 @@ int uart_irq_update(int port)
*
* Returns the IRQ number used by the specified UART port
*
* RETURNS: N/A
* @return N/A
*/
unsigned int uart_irq_get(int port /* UART port */

32
drivers/serial/ns16550.c
View file

@ -263,7 +263,7 @@ UART_PORTS_CONFIGURE(struct ns16550, uart);
*
* This routine is called to reset the chip in a quiescent state.
*
* RETURNS: N/A
* @return N/A
*/
void uart_init(int port, /* UART channel to initialize */
@ -314,7 +314,7 @@ void uart_init(int port, /* UART channel to initialize */
*
* uart_poll_in - poll the device for input.
*
* RETURNS: 0 if a character arrived, -1 if the input buffer if empty.
* @return 0 if a character arrived, -1 if the input buffer if empty.
*/
int uart_poll_in(int port, /* UART channel to select for input */
@ -340,7 +340,7 @@ int uart_poll_in(int port, /* UART channel to select for input */
* If the hardware flow control is enabled then the handshake signal CTS has to
* be asserted in order to send a character.
*
* RETURNS: sent character
* @return sent character
*/
unsigned char uart_poll_out(
int port, /* UART channel to select for output */
@ -361,7 +361,7 @@ unsigned char uart_poll_out(
*
* uart_fifo_fill - fill FIFO with data
*
* RETURNS: number of bytes sent
* @return number of bytes sent
*/
int uart_fifo_fill(int port, /* UART on port to send */
@ -381,7 +381,7 @@ int uart_fifo_fill(int port, /* UART on port to send */
*
* uart_fifo_read - read data from FIFO
*
* RETURNS: number of bytes read
* @return number of bytes read
*/
int uart_fifo_read(int port, /* UART to receive from */
@ -402,7 +402,7 @@ int uart_fifo_read(int port, /* UART to receive from */
*
* uart_irq_tx_enable - enable TX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_tx_enable(int port /* UART to enable Tx
@ -416,7 +416,7 @@ void uart_irq_tx_enable(int port /* UART to enable Tx
*
* uart_irq_tx_disable - disable TX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_tx_disable(int port /* UART to disable Tx interrupt */
@ -429,7 +429,7 @@ void uart_irq_tx_disable(int port /* UART to disable Tx interrupt */
*
* uart_irq_tx_ready - check if Tx IRQ has been raised
*
* RETURNS: N/A
* @return N/A
*/
int uart_irq_tx_ready(int port /* UART to check */
@ -442,7 +442,7 @@ int uart_irq_tx_ready(int port /* UART to check */
*
* _uart_irq_rx_enable - enable RX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_rx_enable(int port /* UART to enable Rx
@ -456,7 +456,7 @@ void uart_irq_rx_enable(int port /* UART to enable Rx
*
* uart_irq_rx_disable - disable RX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_rx_disable(int port /* UART to disable Rx interrupt */
@ -469,7 +469,7 @@ void uart_irq_rx_disable(int port /* UART to disable Rx interrupt */
*
* uart_irq_rx_ready - check if Rx IRQ has been raised
*
* RETURNS: 1 if an IRQ is ready, 0 otherwise
* @return 1 if an IRQ is ready, 0 otherwise
*/
int uart_irq_rx_ready(int port /* UART to check */
@ -482,7 +482,7 @@ int uart_irq_rx_ready(int port /* UART to check */
*
* uart_irq_err_enable - enable error interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_err_enable(int port /* UART to enable Rx interrupt */
@ -495,7 +495,7 @@ void uart_irq_err_enable(int port /* UART to enable Rx interrupt */
*
* uart_irq_err_disable - disable error interrupt in IER
*
* RETURNS: 1 if an IRQ is ready, 0 otherwise
* @return 1 if an IRQ is ready, 0 otherwise
*/
void uart_irq_err_disable(int port /* UART to disable Rx interrupt */
@ -508,7 +508,7 @@ void uart_irq_err_disable(int port /* UART to disable Rx interrupt */
*
* uart_irq_is_pending - check if any IRQ is pending
*
* RETURNS: 1 if an IRQ is pending, 0 otherwise
* @return 1 if an IRQ is pending, 0 otherwise
*/
int uart_irq_is_pending(int port /* UART to check */
@ -521,7 +521,7 @@ int uart_irq_is_pending(int port /* UART to check */
*
* uart_irq_update - update cached contents of IIR
*
* RETURNS: always 1
* @return always 1
*/
int uart_irq_update(int port /* UART to update */
@ -538,7 +538,7 @@ int uart_irq_update(int port /* UART to update */
*
* Returns the IRQ number used by the specified UART port
*
* RETURNS: N/A
* @return N/A
*/
unsigned int uart_irq_get(int port /* UART port */

42
drivers/serial/stellarisUartDrv.c
View file

@ -159,7 +159,7 @@ UART_PORTS_CONFIGURE(struct _StellarisUartPort, ports);
*
* This routine set the given baud rate for the UART.
*
* RETURNS: N/A
* @return N/A
*/
static void baudrateSet(int port, uint32_t baudrate, uint32_t sysClkFreqInHz)
@ -190,7 +190,7 @@ static void baudrateSet(int port, uint32_t baudrate, uint32_t sysClkFreqInHz)
*
* This routine enables the given UART.
*
* RETURNS: N/A
* @return N/A
*/
static inline void enable(int port)
@ -206,7 +206,7 @@ static inline void enable(int port)
*
* This routine disables the given UART.
*
* RETURNS: N/A
* @return N/A
*/
static inline void disable(int port)
@ -239,7 +239,7 @@ static inline void disable(int port)
*
* This routine sets the given UART's line controls to their default settings.
*
* RETURNS: N/A
* @return N/A
*/
static inline void lineControlDefaultsSet(int port)
@ -256,7 +256,7 @@ static inline void lineControlDefaultsSet(int port)
* This routine is called to reset the chip in a quiescent state.
* It is assumed that this function is called only once per UART.
*
* RETURNS: N/A
* @return N/A
*/
void uart_init(int port, /* UART channel to initialize */
const struct uart_init_info * const init_info
@ -276,7 +276,7 @@ void uart_init(int port, /* UART channel to initialize */
*
* This routine returns the given UART's transmit ready status.
*
* RETURNS: 0 if ready to transmit, 1 otherwise
* @return 0 if ready to transmit, 1 otherwise
*/
static int pollTxReady(int port)
@ -290,7 +290,7 @@ static int pollTxReady(int port)
*
* uart_poll_in - poll the device for input.
*
* RETURNS: 0 if a character arrived, -1 if the input buffer if empty.
* @return 0 if a character arrived, -1 if the input buffer if empty.
*/
int uart_poll_in(int port, /* UART channel to select for input */
@ -315,7 +315,7 @@ int uart_poll_in(int port, /* UART channel to select for input */
* Checks if the transmitter is empty. If empty, a character is written to
* the data register.
*
* RETURNS: sent character
* @return sent character
*/
unsigned char uart_poll_out(int port, unsigned char c)
{
@ -335,7 +335,7 @@ unsigned char uart_poll_out(int port, unsigned char c)
*
* uart_fifo_fill - fill FIFO with data
*
* RETURNS: number of bytes sent
* @return number of bytes sent
*/
int uart_fifo_fill(int port, /* UART on which to send */
@ -357,7 +357,7 @@ int uart_fifo_fill(int port, /* UART on which to send */
*
* uart_fifo_read - read data from FIFO
*
* RETURNS: number of bytes read
* @return number of bytes read
*/
int uart_fifo_read(int port, /* UART to receive from */
@ -379,7 +379,7 @@ int uart_fifo_read(int port, /* UART to receive from */
*
* uart_irq_tx_enable - enable TX interrupt
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_tx_enable(int port /* UART to enable Tx interrupt */
@ -434,7 +434,7 @@ void uart_irq_tx_enable(int port /* UART to enable Tx interrupt */
*
* uart_irq_tx_disable - disable TX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_tx_disable(int port /* UART to disable Tx interrupt */
@ -449,7 +449,7 @@ void uart_irq_tx_disable(int port /* UART to disable Tx interrupt */
*
* uart_irq_tx_ready - check if Tx IRQ has been raised
*
* RETURNS: 1 if a Tx IRQ is pending, 0 otherwise
* @return 1 if a Tx IRQ is pending, 0 otherwise
*/
int uart_irq_tx_ready(int port /* UART to check */
@ -464,7 +464,7 @@ int uart_irq_tx_ready(int port /* UART to check */
*
* uart_irq_rx_enable - enable RX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_rx_enable(int port /* UART to enable Rx interrupt */
@ -479,7 +479,7 @@ void uart_irq_rx_enable(int port /* UART to enable Rx interrupt */
*
* uart_irq_rx_disable - disable RX interrupt in IER
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_rx_disable(int port /* UART to disable Rx interrupt */
@ -494,7 +494,7 @@ void uart_irq_rx_disable(int port /* UART to disable Rx interrupt */
*
* uart_irq_rx_ready - check if Rx IRQ has been raised
*
* RETURNS: 1 if an IRQ is ready, 0 otherwise
* @return 1 if an IRQ is ready, 0 otherwise
*/
int uart_irq_rx_ready(int port /* UART to check */
@ -509,7 +509,7 @@ int uart_irq_rx_ready(int port /* UART to check */
*
* uart_irq_err_enable - enable error interrupts
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_err_enable(int port /* UART to enable interrupts for */
@ -525,7 +525,7 @@ void uart_irq_err_enable(int port /* UART to enable interrupts for */
*
* uart_irq_err_disable - disable error interrupts
*
* RETURNS: N/A
* @return N/A
*/
void uart_irq_err_disable(int port /* UART to disable interrupts for */
@ -541,7 +541,7 @@ void uart_irq_err_disable(int port /* UART to disable interrupts for */
*
* uart_irq_is_pending - check if Tx or Rx IRQ is pending
*
* RETURNS: 1 if a Tx or Rx IRQ is pending, 0 otherwise
* @return 1 if a Tx or Rx IRQ is pending, 0 otherwise
*/
int uart_irq_is_pending(int port /* UART to check */
@ -557,7 +557,7 @@ int uart_irq_is_pending(int port /* UART to check */
*
* uart_irq_update - update IRQ status
*
* RETURNS: always 1
* @return always 1
*/
int uart_irq_update(int port)
@ -571,7 +571,7 @@ int uart_irq_update(int port)
*
* Returns the IRQ number used by the specified UART port
*
* RETURNS: N/A
* @return N/A
*/
unsigned int uart_irq_get(int port /* UART port */

14
drivers/timer/arcv2_timer0.c
View file

@ -77,7 +77,7 @@ static uint32_t clock_accumulated_count = 0;
* - setting the timer's start value to zero; and
* - enabling interrupt generation.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -102,7 +102,7 @@ static ALWAYS_INLINE void enable(
* This routine gets the value from the timer's count register. This
* value is the 'time' elapsed from the starting count (assumed to be 0).
*
* RETURNS: the current counter value
* @return the current counter value
*
* \NOMANUAL
*/
@ -118,7 +118,7 @@ static ALWAYS_INLINE uint32_t count_get(void)
* This routine gets the value from the timer's limit register, which is the
* value to which the timer will count up to.
*
* RETURNS: the limit value
* @return the limit value
*
* \NOMANUAL
*/
@ -134,7 +134,7 @@ static ALWAYS_INLINE uint32_t limit_get(void)
* This routine handles the system clock periodic tick interrupt. A TICK_EVENT
* event is pushed onto the microkernel stack.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -160,7 +160,7 @@ void _timer_int_handler(void *unused)
* This routine is used to program the ARCv2 timer to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* RETURNS: N/A
* @return N/A
*/
void timer_driver(
@ -195,7 +195,7 @@ void timer_driver(
*
* This routine returns the current time in terms of timer hardware clock cycles.
*
* RETURNS: up counter of elapsed clock cycles
* @return up counter of elapsed clock cycles
*/
uint32_t timer_read(void)
@ -211,7 +211,7 @@ uint32_t timer_read(void)
* This routine disables timer interrupt generation and delivery.
* Note that the timer's counting cannot be stopped by software.
*
* RETURNS: N/A
* @return N/A
*/
void timer_disable(void)

24
drivers/timer/cortex_m_timer.c
View file

@ -133,7 +133,7 @@ static unsigned char idle_mode = IDLE_NOT_TICKLESS;
*
* This routine disables the systick counter.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -162,7 +162,7 @@ static ALWAYS_INLINE void sysTickStop(void)
*
* This routine enables the systick counter.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -191,7 +191,7 @@ static ALWAYS_INLINE void sysTickStart(void)
* value is the 'time' remaining to decrement before the timer triggers an
* interrupt.
*
* RETURNS: the current counter value
* @return the current counter value
*
* \NOMANUAL
*/
@ -206,7 +206,7 @@ static ALWAYS_INLINE uint32_t sysTickCurrentGet(void)
*
* This routine returns the value from the reload value register.
*
* RETURNS: the counter's initial count/wraparound value
* @return the counter's initial count/wraparound value
*
* \NOMANUAL
*/
@ -225,7 +225,7 @@ static ALWAYS_INLINE uint32_t sysTickReloadGet(void)
* sets the timer's current value register to zero.
* Note that the value given is assumed to be valid (i.e., count < (1<<24)).
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -254,7 +254,7 @@ static ALWAYS_INLINE void sysTickReloadSet(
* The symbol for this routine is either _timer_int_handler (for normal
* system operation) or _real_timer_int_handler (when GDB_INFO is enabled).
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -390,7 +390,7 @@ void _TIMER_INT_HANDLER(void *unused)
* Conversely, the smaller the value (the higher the tick frequency), the
* more elapsed ticks during a "tickless idle".
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -467,7 +467,7 @@ static void sysTickTicklessIdleInit(void)
* ticks supplied or the maximum number of ticks that can be programmed into
* hardware. A value of -1 will result in the maximum number of ticks.
*
* RETURNS: N/A
* @return N/A
*/
void _timer_idle_enter(int32_t ticks /* system ticks */
@ -526,7 +526,7 @@ void _timer_idle_enter(int32_t ticks /* system ticks */
* ticker has done its work and consumed all the ticks. This has to be true
* otherwise idle mode wouldn't have been entered in the first place.
*
* RETURNS: N/A
* @return N/A
*/
void _timer_idle_exit(void)
@ -613,7 +613,7 @@ void _timer_idle_exit(void)
* This routine is used to program the systick to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* RETURNS: N/A
* @return N/A
*/
void timer_driver(int priority /* priority parameter is ignored by this driver
*/
@ -654,7 +654,7 @@ void timer_driver(int priority /* priority parameter is ignored by this driver
* Some kernel facilities (e.g. benchmarking code) directly call timer_read()
* instead of utilizing the 'timer_read_fptr' function pointer.
*
* RETURNS: up counter of elapsed clock cycles
* @return up counter of elapsed clock cycles
*
* \INTERNAL WARNING
* systick counter is a 24-bit down counter which is reset to "reload" value
@ -675,7 +675,7 @@ uint32_t timer_read(void)
* This routine disables the systick so that timer interrupts are no
* longer delivered.
*
* RETURNS: N/A
* @return N/A
*/
void timer_disable(void)

14
drivers/timer/hpet.c
View file

@ -228,7 +228,7 @@ static int stale_irq_check =
* of the counter is read twice to ensure it doesn't change while the least
* significant word is being retrieved (as per HPET documentation).
*
* RETURNS: current 64-bit counter value
* @return current 64-bit counter value
*
* \NOMANUAL
*/
@ -255,7 +255,7 @@ static uint64_t _hpetMainCounterAtomic(void)
* This routine handles the system clock tick interrupt. A TICK_EVENT event
* is pushed onto the microkernel stack.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -356,7 +356,7 @@ void _timer_int_handler(void *unused)
* Re-program the timer to enter into the idle state for the given number of
* ticks (-1 means infinite number of ticks).
*
* RETURNS: N/A
* @return N/A
*
* \INTERNAL IMPLEMENTATION DETAILS
* Called while interrupts are locked.
@ -389,7 +389,7 @@ void _timer_idle_enter(int32_t ticks /* system ticks */
* ticker has done its work and consumed all the ticks. This has to be true
* otherwise idle mode wouldn't have been entered in the first place.
*
* RETURNS: N/A
* @return N/A
*
* \INTERNAL IMPLEMENTATION DETAILS
* Called by _IntEnt() while interrupts are locked.
@ -494,7 +494,7 @@ void _timer_idle_exit(void)
* This routine is used to program the HPET to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* RETURNS: N/A
* @return N/A
*/
void timer_driver(int priority /* priority parameter is ignored by this driver
@ -626,7 +626,7 @@ void timer_driver(int priority /* priority parameter is ignored by this driver
*
* This routine returns the current time in terms of timer hardware clock cycles.
*
* RETURNS: up counter of elapsed clock cycles
* @return up counter of elapsed clock cycles
*
* \INTERNAL WARNING
* If this routine is ever enhanced to return all 64 bits of the counter
@ -647,7 +647,7 @@ uint32_t timer_read(void)
* This routine disables the HPET so that timer interrupts are no
* longer delivered.
*
* RETURNS: N/A
* @return N/A
*/
void timer_disable(void)

22
drivers/timer/i8253.c
View file

@ -148,7 +148,7 @@ extern struct nano_stack _k_command_stack;
*
* This routine reads the 16 bit value from the i8253 counter register.
*
* RETURNS: counter register's 16 bit value
* @return counter register's 16 bit value
*
* \NOMANUAL
*/
@ -176,7 +176,7 @@ static inline uint16_t _i8253CounterRead(void)
* This routine sets the 16 bit value from which the i8253 timer will
* decrement and sets that counter register to its value.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -198,7 +198,7 @@ static inline void _i8253CounterSet(
*
* This routine sets the i8253 to fire on a periodic basis.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -218,7 +218,7 @@ static inline void _i8253CounterPeriodic(
*
* This routine sets the i8253 to fire once only.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -239,7 +239,7 @@ static inline void _i8253CounterOneShot(
* This routine handles the system clock periodic tick interrupt. A TICK_EVENT
* event is pushed onto the microkernel stack.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -316,7 +316,7 @@ void _timer_int_handler(void *unusedArg /* not used */
* value (the higher the tick frequency), the more elapsed ticks during a
* "tickless idle".
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -332,7 +332,7 @@ static void _i8253TicklessIdleInit(void)
*
* _i8253TicklessIdleSkew -
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -413,7 +413,7 @@ void _timer_idle_enter(int32_t ticks /* system ticks */
*
* Called in _IntEnt()
*
* RETURNS: N/A
* @return N/A
*/
void _timer_idle_exit(void)
@ -473,7 +473,7 @@ void _timer_idle_exit(void)
* This routine is used to program the PIT to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* RETURNS: N/A
* @return N/A
*/
void timer_driver(int priority /* priority parameter ignored by this driver */
@ -507,7 +507,7 @@ void timer_driver(int priority /* priority parameter ignored by this driver */
*
* This routine returns the current time in terms of timer hardware clock cycles.
*
* RETURNS: up counter of elapsed clock cycles
* @return up counter of elapsed clock cycles
*/
uint32_t timer_read(void)
@ -563,7 +563,7 @@ uint32_t timer_read(void)
* This routine simply disables the PIT counter such that interrupts are no
* longer delivered.
*
* RETURNS: N/A
* @return N/A
*/
void timer_disable(void)

32
drivers/timer/loapic_timer.c
View file

@ -138,7 +138,7 @@ extern struct nano_stack _k_command_stack;
*
* This routine sets the timer for periodic mode.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -157,7 +157,7 @@ static inline void _loApicTimerPeriodic(void)
*
* This routine stops the timer.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -176,7 +176,7 @@ static inline void _loApicTimerStop(void)
*
* This routine starts the timer.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -193,7 +193,7 @@ static inline void _loApicTimerStart(void)
*
* This routine sets value from which the timer will count down.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -212,7 +212,7 @@ static inline void _loApicTimerSetCount(
*
* This routine sets the timer for one shot mode.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -230,7 +230,7 @@ static inline void _loApicTimerOneShot(void)
* This routine sets rate at which the timer is decremented to match the
* external bus frequency.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -248,7 +248,7 @@ static inline void _loApicTimerSetDivider(void)
* value is the 'time' remaining to decrement before the timer triggers an
* interrupt.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -264,7 +264,7 @@ static inline uint32_t _loApicTimerGetRemaining(void)
*
* This routine gets the value from the initial count register.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -281,7 +281,7 @@ static inline uint32_t _loApicTimerGetCount(void)
* This routine handles the system clock tick interrupt. A TICK_EVENT event
* is pushed onto the microkernel stack.
*
* RETURNS: N/A
* @return N/A
*/
void _timer_int_handler(void *unused /* parameter is not used */
@ -361,7 +361,7 @@ void _timer_int_handler(void *unused /* parameter is not used */
* value (the higher the tick frequency), the more elapsed ticks during a
* "tickless idle".
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -384,7 +384,7 @@ static void _loApicTimerTicklessIdleInit(void)
* 3. Set timer mode to periodic/one-shot
* 4. Start timer.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -416,7 +416,7 @@ static void _loApicTimerTicklessIdleSkew(void)
* ticks supplied or the maximum number of ticks that can be programmed into
* hardware. A value of -1 means inifinite number of ticks.
*
* RETURNS: N/A
* @return N/A
*/
void _timer_idle_enter(int32_t ticks /* system ticks */
@ -473,7 +473,7 @@ void _timer_idle_enter(int32_t ticks /* system ticks */
*
* Called in _IntEnt()
*
* RETURNS: N/A
* @return N/A
*/
void _timer_idle_exit(void)
@ -537,7 +537,7 @@ void _timer_idle_exit(void)
* This routine is used to program the PIT to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* RETURNS: N/A
* @return N/A
*/
void timer_driver(int priority /* priority parameter ignored by this driver */
@ -576,7 +576,7 @@ void timer_driver(int priority /* priority parameter ignored by this driver */
*
* This routine returns the current time in terms of timer hardware clock cycles.
*
* RETURNS: up counter of elapsed clock cycles
* @return up counter of elapsed clock cycles
*/
uint32_t timer_read(void)
@ -606,7 +606,7 @@ uint32_t timer_read(void)
* This routine simply disables the LOAPIC counter such that interrupts are no
* longer delivered.
*
* RETURNS: N/A
* @return N/A
*/
void timer_disable(void)

8
include/arch/arc/v2/arcv2_irq_unit.h
View file

@ -65,7 +65,7 @@
*
* Enables or disables the specified interrupt
*
* RETURNS: N/A
* @return N/A
*/
static inline void _arc_v2_irq_unit_irq_enable_set(
@ -82,7 +82,7 @@ static inline void _arc_v2_irq_unit_irq_enable_set(
*
* Enables the specified interrupt
*
* RETURNS: N/A
* @return N/A
*/
static inline void _arc_v2_irq_unit_int_enable(int irq)
@ -95,7 +95,7 @@ static inline void _arc_v2_irq_unit_int_enable(int irq)
*
* Disables the specified interrupt
*
* RETURNS: N/A
* @return N/A
*/
static inline void _arc_v2_irq_unit_int_disable(int irq)
@ -108,7 +108,7 @@ static inline void _arc_v2_irq_unit_int_disable(int irq)
*
* Set the priority of the specified interrupt
*
* RETURNS: N/A
* @return N/A
*/
static inline void _arc_v2_irq_unit_prio_set(int irq, unsigned char prio)

4
include/arch/arc/v2/ffs.h
View file

@ -54,7 +54,7 @@ extern unsigned nanoFfsMsb(unsigned int);
* significant bit. A return value of zero indicates that the value passed
* is zero.
*
* RETURNS: most significant bit set
* @return most significant bit set
*/
#if defined(__GNUC__)
@ -83,7 +83,7 @@ static ALWAYS_INLINE unsigned int nanoFfsMsb_inline(unsigned int op)
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: least significant bit set
* @return least significant bit set
*/
#if defined(__GNUC__)

4
include/arch/arc/v2/irq.h
View file

@ -77,7 +77,7 @@ extern void _irq_exit(void);
*
* See irq_lock() for full description
*
* RETURNS: An architecture-dependent lock-out key representing the
* @return An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
@ -97,7 +97,7 @@ static ALWAYS_INLINE unsigned int irq_lock_inline(void)
*
* See irq_unlock() for full description
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

8
include/arch/arm/CortexM/asm_inline_gcc.h
View file

@ -61,7 +61,7 @@
* significant bit. A return value of zero indicates that the value passed
* is zero.
*
* RETURNS: most significant bit set
* @return most significant bit set
*/
static ALWAYS_INLINE unsigned int find_last_set_inline(unsigned int op)
@ -89,7 +89,7 @@ static ALWAYS_INLINE unsigned int find_last_set_inline(unsigned int op)
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: least significant bit set
* @return least significant bit set
*/
static ALWAYS_INLINE unsigned int find_first_set_inline(unsigned int op)
@ -134,7 +134,7 @@ static ALWAYS_INLINE unsigned int find_first_set_inline(unsigned int op)
* disable state will be restored when the context is later rescheduled
* for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* @return An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
@ -166,7 +166,7 @@ static ALWAYS_INLINE unsigned int irq_lock_inline(void)
*
* This routine can be called from either interrupt, task or fiber level.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

4
include/arch/arm/CortexM/irq.h
View file

@ -88,7 +88,7 @@ extern void _IntExit(void);
* <priority> with the interrupt routine <isr>, that receives parameter
* <parameter>
*
* RETURNS: N/A
* @return N/A
*
*/
#define IRQ_CONNECT_STATIC(device, irq, priority, isr, parameter) \
@ -104,7 +104,7 @@ extern void _IntExit(void);
* For the given device do the neccessary configuration steps.
* Fpr ARM platform, set the interrupt priority
*
* RETURNS: N/A
* @return N/A
*
*/
#define IRQ_CONFIG(device, irq) irq_priority_set(irq, _##device##_int_priority)

18
include/arch/arm/CortexM/nvic.h
View file

@ -91,7 +91,7 @@ Supports up to 240 IRQs and 256 priority levels.
*
* Enable IRQ #<irq>, which is equivalent to exception #<irq>+16
*
* RETURNS: N/A
* @return N/A
*/
static inline void _NvicIrqEnable(unsigned int irq /* IRQ number */
@ -106,7 +106,7 @@ static inline void _NvicIrqEnable(unsigned int irq /* IRQ number */
*
* Find out if IRQ #<irq> is enabled.
*
* RETURNS: 1 if IRQ is enabled, 0 otherwise
* @return 1 if IRQ is enabled, 0 otherwise
*/
static inline int _NvicIsIrqEnabled(unsigned int irq /* IRQ number */
@ -121,7 +121,7 @@ static inline int _NvicIsIrqEnabled(unsigned int irq /* IRQ number */
*
* Disable IRQ #<irq>, which is equivalent to exception #<irq>+16
*
* RETURNS: N/A
* @return N/A
*/
static inline void _NvicIrqDisable(unsigned int irq /* IRQ number */
@ -138,7 +138,7 @@ static inline void _NvicIrqDisable(unsigned int irq /* IRQ number */
* the IRQ when interrupts are enabled and/or returning from a higher priority
* interrupt.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _NvicIrqPend(unsigned int irq /* IRQ number */
@ -153,7 +153,7 @@ static inline void _NvicIrqPend(unsigned int irq /* IRQ number */
*
* Find out if IRQ #<irq> is pending
*
* RETURNS: 1 if IRQ is pending, 0 otherwise
* @return 1 if IRQ is pending, 0 otherwise
*/
static inline int _NvicIsIrqPending(unsigned int irq /* IRQ number */
@ -170,7 +170,7 @@ static inline int _NvicIsIrqPending(unsigned int irq /* IRQ number */
* pending interrupt will be ignored when either unlocking interrupts or
* returning from a higher priority exception.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _NvicIrqUnpend(unsigned int irq /* IRQ number */
@ -185,7 +185,7 @@ static inline void _NvicIrqUnpend(unsigned int irq /* IRQ number */
*
* Set priority of IRQ #<irq> to <prio>. There are 256 priority levels.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _NvicIrqPrioSet(unsigned int irq, /* IRQ number */
@ -202,7 +202,7 @@ static inline void _NvicIrqPrioSet(unsigned int irq, /* IRQ number */
*
* Get priority of IRQ #<irq>.
*
* RETURNS: the priority level of the IRQ
* @return the priority level of the IRQ
*/
static inline uint32_t _NvicIrqPrioGet(unsigned int irq /* IRQ number */
@ -218,7 +218,7 @@ static inline uint32_t _NvicIrqPrioGet(unsigned int irq /* IRQ number */
* Trigger interrupt #<irq>. The CPU will handle the IRQ when interrupts are
* enabled and/or returning from a higher priority interrupt.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _NvicSwInterruptTrigger(unsigned int irq /* IRQ number */

152
include/arch/arm/CortexM/scb.h
View file

@ -77,7 +77,7 @@ extern void _ScbNumPriGroupSet(unsigned int n);
*
* _ScbIsNmiPending - find out if the NMI exception is pending
*
* RETURNS: 1 if it is pending, 0 otherwise
* @return 1 if it is pending, 0 otherwise
*/
static inline int _ScbIsNmiPending(void)
@ -91,7 +91,7 @@ static inline int _ScbIsNmiPending(void)
*
* Pend the NMI exception: it should fire immediately.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbNmiPend(void)
@ -103,7 +103,7 @@ static inline void _ScbNmiPend(void)
*
* _ScbIsPendsvPending - find out if the PendSV exception is pending
*
* RETURNS: 1 if it is pending, 0 otherwise
* @return 1 if it is pending, 0 otherwise
*/
static inline int _ScbIsPendsvPending(void)
@ -118,7 +118,7 @@ static inline int _ScbIsPendsvPending(void)
* Set the PendSV exception: it will be handled when the last nested exception
* returns, or immediately if running in thread mode.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbPendsvSet(void)
@ -132,7 +132,7 @@ static inline void _ScbPendsvSet(void)
*
* This routine clears the PendSV exception.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbPendsvClear(void)
@ -146,7 +146,7 @@ static inline void _ScbPendsvClear(void)
*
* This routine determines if the SYSTICK exception is pending.
*
* RETURNS: 1 if it is pending, 0 otherwise
* @return 1 if it is pending, 0 otherwise
*/
static inline int _ScbIsSystickPending(void)
@ -162,7 +162,7 @@ static inline int _ScbIsSystickPending(void)
* priority exception or immediately if in thread mode or handling a lower
* priority exception.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSystickPendSet(void)
@ -176,7 +176,7 @@ static inline void _ScbSystickPendSet(void)
*
* This routine clears the SYSTICK exception.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSystickPendClear(void)
@ -190,7 +190,7 @@ static inline void _ScbSystickPendClear(void)
*
* Find out if an external interrupt, generated by the NVIC, is pending.
*
* RETURNS: 1 if one or more interrupt is pending, 0 otherwise
* @return 1 if one or more interrupt is pending, 0 otherwise
*/
static inline int _ScbIsIrqPending(void)
@ -206,7 +206,7 @@ static inline int _ScbIsIrqPending(void)
* If one or more exceptions are pending, return the exception number of the
* highest-priority one; otherwise, return 0.
*
* RETURNS: the exception number if one is pending, 0 otherwise
* @return the exception number if one is pending, 0 otherwise
*/
static inline int _ScbHiPriVectorPendingGet(void)
@ -223,7 +223,7 @@ static inline int _ScbHiPriVectorPendingGet(void)
*
* This routine determines if the currently executing exception is nested.
*
* RETURNS: 1 if nested, 0 otherwise
* @return 1 if nested, 0 otherwise
*/
static inline int _ScbIsNestedExc(void)
@ -238,7 +238,7 @@ static inline int _ScbIsNestedExc(void)
*
* This routine determines if the current mode is thread mode.
*
* RETURNS: 1 if in thread mode, 0 otherwise
* @return 1 if in thread mode, 0 otherwise
*/
static inline int _ScbIsInThreadMode(void)
@ -253,7 +253,7 @@ static inline int _ScbIsInThreadMode(void)
*
* This routine determines if the current mode is handler mode.
*
* RETURNS: 1 if in handler mode, 0 otherwise
* @return 1 if in handler mode, 0 otherwise
*/
static inline int _ScbIsInHandlerMode(void)
@ -267,7 +267,7 @@ static inline int _ScbIsInHandlerMode(void)
*
* This routine determines if an exception is being handled (handler mode).
*
* RETURNS: 1 if handling an exception, 0 otherwise
* @return 1 if handling an exception, 0 otherwise
*/
static inline int _ScbIsInExc(void)
@ -282,7 +282,7 @@ static inline int _ScbIsInExc(void)
* If currently handling an exception/interrupt, return the exceuting vector
* number. If not, return 0.
*
* RETURNS: the currently excecuting vector number, 0 if in thread mode.
* @return the currently excecuting vector number, 0 if in thread mode.
*/
static inline uint32_t _ScbActiveVectorGet(void)
@ -296,7 +296,7 @@ static inline uint32_t _ScbActiveVectorGet(void)
*
* This routine determines if the currently executing exception is nested.
*
* RETURNS: 1 if in SRAM, 0 if in ROM
* @return 1 if in SRAM, 0 if in ROM
*/
static inline uint32_t _ScbIsVtableInSram(void)
@ -310,7 +310,7 @@ static inline uint32_t _ScbIsVtableInSram(void)
*
* This routine moves the vector table to the given memory region.
*
* RETURNS: 1 if in SRAM, 0 if in ROM
* @return 1 if in SRAM, 0 if in ROM
*/
static inline void _ScbVtableLocationSet(
@ -327,7 +327,7 @@ static inline void _ScbVtableLocationSet(
*
* This routine returs the vector table's base address.
*
* RETURNS: the base address of the vector table
* @return the base address of the vector table
*/
static inline uint32_t _ScbVtableAddrGet(void)
@ -350,7 +350,7 @@ static inline uint32_t _ScbVtableAddrGet(void)
* 48 <= num_interrupts < 112: multiple 0x200
* ....
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbVtableAddrSet(uint32_t addr /* base address, aligned on
@ -368,7 +368,7 @@ static inline void _ScbVtableAddrSet(uint32_t addr /* base address, aligned on
* Data regions on Cortex-M devices can be either little or big endian. Code
* regions are always little endian.
*
* RETURNS: 1 if little endian, 0 if big endian
* @return 1 if little endian, 0 if big endian
*/
static inline int _ScbIsDataLittleEndian(void)
@ -384,7 +384,7 @@ static inline int _ScbIsDataLittleEndian(void)
* Within these groups, exceptions do not preempt each other. The sub-priorities
* are only used to decide which exception will run when several are pending.
*
* RETURNS: the number of priority groups
* @return the number of priority groups
*/
static inline int _ScbNumPriGroupGet(void)
@ -400,7 +400,7 @@ static inline int _ScbNumPriGroupGet(void)
*
* This enables the feature until it is cancelled.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSleepOnExitSet(void)
@ -415,7 +415,7 @@ static inline void _ScbSleepOnExitSet(void)
* This routine prevents CPU sleep mode upon exiting an ISR.
* This is the normal operating mode.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSleepOnExitClear(void)
@ -436,7 +436,7 @@ static inline void _ScbSleepOnExitClear(void)
*
* This enables the feature until it is cancelled.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSevOnPendSet(void)
@ -450,7 +450,7 @@ static inline void _ScbSevOnPendSet(void)
*
* See _ScbSevOnPendSet().
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSevOnPendClear(void)
@ -467,7 +467,7 @@ static inline void _ScbSevOnPendClear(void)
*
* Behaviour is processor-specific.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSleepDeepSet(void)
@ -481,7 +481,7 @@ static inline void _ScbSleepDeepSet(void)
*
* This routine prevents CPU deep sleep mode.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbSleepDeepClear(void)
@ -496,7 +496,7 @@ static inline void _ScbSleepDeepClear(void)
* This routine enables the divide by zero fault.
* By default, the CPU ignores the error.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbDivByZeroFaultEnable(void)
@ -511,7 +511,7 @@ static inline void _ScbDivByZeroFaultEnable(void)
* This routine disables the divide by zero fault.
* This is the default behaviour.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbDivByZeroFaultDisable(void)
@ -526,7 +526,7 @@ static inline void _ScbDivByZeroFaultDisable(void)
* This routine enables the unaligned access fault.
* By default, the CPU ignores the error.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUnalignedFaultEnable(void)
@ -541,7 +541,7 @@ static inline void _ScbUnalignedFaultEnable(void)
* This routine disables the divide by zero fault.
* This is the default behaviour.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUnalignedFaultDisable(void)
@ -555,7 +555,7 @@ static inline void _ScbUnalignedFaultDisable(void)
*
* This routine writes the given value to the Configuration Control Register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void ScbCcrSet(uint32_t val /* value to write to CCR */
@ -573,7 +573,7 @@ static inline void ScbCcrSet(uint32_t val /* value to write to CCR */
*
* Exceptions 1 to 3 priorities are fixed (-3, -2, -1).
*
* RETURNS: priority of exception <exc>
* @return priority of exception <exc>
*/
static inline uint8_t _ScbExcPrioGet(uint8_t exc /* exception number, 4 to 15 */
@ -596,7 +596,7 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc /* exception number, 4 to 15 */
*
* Exceptions 1 to 3 priorities are fixed (-3, -2, -1).
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbExcPrioSet(uint8_t exc, /* exception number, 4 to 15 */
@ -615,7 +615,7 @@ static inline void _ScbExcPrioSet(uint8_t exc, /* exception number, 4 to 15 */
* This routine enables usage faults.
* By default, the CPU does not raise usage fault exceptions.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultEnable(void)
@ -630,7 +630,7 @@ static inline void _ScbUsageFaultEnable(void)
* This routine disables usage faults.
* This is the default behaviour.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultDisable(void)
@ -645,7 +645,7 @@ static inline void _ScbUsageFaultDisable(void)
* This routine enables bus faults.
* By default, the CPU does not raise bus fault exceptions.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbBusFaultEnable(void)
@ -660,7 +660,7 @@ static inline void _ScbBusFaultEnable(void)
* This routine disables bus faults.
* This is the default behaviour.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbBusFaultDisable(void)
@ -675,7 +675,7 @@ static inline void _ScbBusFaultDisable(void)
* This routine enables the MPU faults.
* By default, the CPU does not raise MPU fault exceptions.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbMemFaultEnable(void)
@ -690,7 +690,7 @@ static inline void _ScbMemFaultEnable(void)
* This routine disables MPU faults.
* This is the default behaviour.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbMemFaultDisable(void)
@ -706,7 +706,7 @@ static inline void _ScbMemFaultDisable(void)
* This routine determines if a hard fault is caused by a bus error during
* a vector table read operation.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbHardFaultIsBusErrOnVectorRead(void)
@ -721,7 +721,7 @@ static inline int _ScbHardFaultIsBusErrOnVectorRead(void)
* Happens if a fault cannot be triggered because of priority or because it was
* disabled.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbHardFaultIsForced(void)
@ -735,7 +735,7 @@ static inline int _ScbHardFaultIsForced(void)
*
* HFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbHardFaultAllFaultsReset(void)
@ -749,7 +749,7 @@ static inline int _ScbHardFaultAllFaultsReset(void)
*
* This routine determines if a hard fault is an MPU fault.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbIsMemFault(void)
@ -764,7 +764,7 @@ static inline int _ScbIsMemFault(void)
*
* The MMFAR register contains the faulting address on an MPU fault.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsMmfarValid(void)
@ -779,7 +779,7 @@ static inline int _ScbMemFaultIsMmfarValid(void)
* This routine invalidates the MMFAR value. This should be done after
* processing an MPU fault.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbMemFaultMmfarReset(void)
@ -793,7 +793,7 @@ static inline void _ScbMemFaultMmfarReset(void)
*
* CFSR/MMFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline void _ScbMemFaultAllFaultsReset(void)
@ -808,7 +808,7 @@ static inline void _ScbMemFaultAllFaultsReset(void)
* This routine determines if an MPU fault is a stacking fault.
* This may occur upon exception entry.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsStacking(void)
@ -823,7 +823,7 @@ static inline int _ScbMemFaultIsStacking(void)
* This routine determines if an MPU fault is an unstacking fault.
* This may occur upon exception exit.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsUnstacking(void)
@ -839,7 +839,7 @@ static inline int _ScbMemFaultIsUnstacking(void)
* If this routine returns 1, read the MMFAR register via _ScbMemFaultAddrGet()
* to get the faulting address.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsDataAccessViolation(void)
@ -855,7 +855,7 @@ static inline int _ScbMemFaultIsDataAccessViolation(void)
* This routine determines if an MPU fault is due to an instruction access
* violation.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsInstrAccessViolation(void)
@ -867,7 +867,7 @@ static inline int _ScbMemFaultIsInstrAccessViolation(void)
*
* _ScbMemFaultAddrGet - find out the faulting address on an MPU fault
*
* RETURNS: the faulting address
* @return the faulting address
*/
static inline uint32_t _ScbMemFaultAddrGet(void)
@ -881,7 +881,7 @@ static inline uint32_t _ScbMemFaultAddrGet(void)
*
* This routine determines if a hard fault is a bus fault.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbIsBusFault(void)
@ -896,7 +896,7 @@ static inline int _ScbIsBusFault(void)
*
* The BFAR register contains the faulting address on bus fault.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsBfarValid(void)
@ -911,7 +911,7 @@ static inline int _ScbBusFaultIsBfarValid(void)
* This routine clears/invalidates the Bus Fault Address Register.
* It should be done after processing a bus fault.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbBusFaultBfarReset(void)
@ -925,7 +925,7 @@ static inline void _ScbBusFaultBfarReset(void)
*
* CFSR/BFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbBusFaultAllFaultsReset(void)
@ -940,7 +940,7 @@ static inline void _ScbBusFaultAllFaultsReset(void)
* This routine determines if a bus fault is a stacking fault.
* This may occurs upon exception entry.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsStacking(void)
@ -955,7 +955,7 @@ static inline int _ScbBusFaultIsStacking(void)
* This routine determines if a bus fault is an unstacking fault.
* This may occur upon exception exit.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsUnstacking(void)
@ -969,7 +969,7 @@ static inline int _ScbBusFaultIsUnstacking(void)
*
* This routine determines if a bus fault is an imprecise error.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsImprecise(void)
@ -984,7 +984,7 @@ static inline int _ScbBusFaultIsImprecise(void)
* Read the BFAR register via _ScbBusFaultAddrGet() if this routine returns 1,
* as it will contain the faulting address.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsPrecise(void)
@ -1000,7 +1000,7 @@ static inline int _ScbBusFaultIsPrecise(void)
* This routine determines if a bus fault is an instruction bus error.
* It is signalled only if the instruction is issued.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsInstrBusErr(void)
@ -1014,7 +1014,7 @@ static inline int _ScbBusFaultIsInstrBusErr(void)
*
* This routine returns the faulting address for a precise bus fault.
*
* RETURNS: the faulting address
* @return the faulting address
*/
static inline uint32_t _ScbBusFaultAddrGet(void)
@ -1028,7 +1028,7 @@ static inline uint32_t _ScbBusFaultAddrGet(void)
*
* This routine determines if a hard fault is a usage fault.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbIsUsageFault(void)
@ -1043,7 +1043,7 @@ static inline int _ScbIsUsageFault(void)
*
* This routine determines if a usage fault is a 'divde by zero' fault.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsDivByZero(void)
@ -1058,7 +1058,7 @@ static inline int _ScbUsageFaultIsDivByZero(void)
*
* This routine determines if a usage fault is an unaligned access error.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsUnaligned(void)
@ -1074,7 +1074,7 @@ static inline int _ScbUsageFaultIsUnaligned(void)
* This routine determines if a usage fault is caused by a coprocessor access.
* This happens if the coprocessor is either absent or disabled.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsNoCp(void)
@ -1090,7 +1090,7 @@ static inline int _ScbUsageFaultIsNoCp(void)
* Happens if the the instruction address on an exception return is not
* halfword-aligned.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsInvalidPcLoad(void)
@ -1107,7 +1107,7 @@ static inline int _ScbUsageFaultIsInvalidPcLoad(void)
* POP, or if the instruction address installed in a exception vector, does not
* have bit 0 set, ie., is not halfword-aligned.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsInvalidState(void)
@ -1122,7 +1122,7 @@ static inline int _ScbUsageFaultIsInvalidState(void)
*
* The processor tried to execute an invalid opcode.
*
* RETURNS: 1 if so, 0 otherwise
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsUndefinedInstr(void)
@ -1136,7 +1136,7 @@ static inline int _ScbUsageFaultIsUndefinedInstr(void)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultDivByZeroReset(void)
@ -1150,7 +1150,7 @@ static inline void _ScbUsageFaultDivByZeroReset(void)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultUnalignedReset(void)
@ -1164,7 +1164,7 @@ static inline void _ScbUsageFaultUnalignedReset(void)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultNoCpReset(void)
@ -1178,7 +1178,7 @@ static inline void _ScbUsageFaultNoCpReset(void)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultInvalidPcLoadReset(void)
@ -1192,7 +1192,7 @@ static inline void _ScbUsageFaultInvalidPcLoadReset(void)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultInvalidStateReset(void)
@ -1206,7 +1206,7 @@ static inline void _ScbUsageFaultInvalidStateReset(void)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultUndefinedInstrReset(void)
@ -1220,7 +1220,7 @@ static inline void _ScbUsageFaultUndefinedInstrReset(void)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScbUsageFaultAllFaultsReset(void)

14
include/arch/arm/CortexM/scs.h
View file

@ -435,7 +435,7 @@ extern volatile struct __scs __scs;
*
* _ScsNumIrqGet - obtain the number of interrupt lines on the target
*
* RETURNS: the number of interrupts
* @return the number of interrupts
*/
static inline int _ScsNumIrqGet(void)
@ -453,7 +453,7 @@ static inline int _ScsNumIrqGet(void)
* they must complete before the processor can stack the current state and invoke
* the interrupt handler.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScsIntMultiCycleInstDisable(void)
@ -467,7 +467,7 @@ static inline void _ScsIntMultiCycleInstDisable(void)
*
* See _ScsIntMultiCycleInstDisable().
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScsIntMultiCycleInstEnable(void)
@ -485,7 +485,7 @@ static inline void _ScsIntMultiCycleInstEnable(void)
* BusFaults to be precise BusFaults but decreases performance because any store
* to memory must complete before the processor can execute the next instruction.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScsWriteBufDisable(void)
@ -499,7 +499,7 @@ static inline void _ScsWriteBufDisable(void)
*
* See _ScsWriteBufDisable().
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScsWriteBufEnable(void)
@ -519,7 +519,7 @@ static inline void _ScsWriteBufEnable(void)
* jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1
* before executing the task, to disable IT folding.
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScsFoldItDisable(void)
@ -533,7 +533,7 @@ static inline void _ScsFoldItDisable(void)
*
* See _ScsFoldItDisable().
*
* RETURNS: N/A
* @return N/A
*/
static inline void _ScsFoldItEnable(void)

10
include/arch/x86/arch.h
View file

@ -122,7 +122,7 @@ typedef struct s_isrList {
* descriptor; (hardware) interrupts and exceptions should specify a level of 0,
* whereas handlers for user-mode software generated interrupts should specify 3.
*
* RETURNS: N/A
* @return N/A
*
*/
@ -146,7 +146,7 @@ typedef struct s_isrList {
* <priority> with the interrupt routine <isr>, that receives parameter
* <parameter>
*
* RETURNS: N/A
* @return N/A
*
*/
#define IRQ_CONNECT_STATIC(device, irq, priority, isr, parameter) \
@ -162,7 +162,7 @@ typedef struct s_isrList {
* For the given device do the neccessary configuration steps.
* For x86 platform configure APIC and mark interrupt vector allocated
*
* RETURNS: N/A
* @return N/A
*
*/
#define IRQ_CONFIG(device, irq) \
@ -299,7 +299,7 @@ void _int_latency_stop(void);
* disable state will be restored when the context is later rescheduled
* for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* @return An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
@ -328,7 +328,7 @@ static inline __attribute__((always_inline))
*
* This routine can be called from either interrupt, task or fiber level.
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/

22
include/arch/x86/asm_inline_gcc.h
View file

@ -69,7 +69,7 @@
* disable state will be restored when the context is later rescheduled
* for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* @return An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
@ -100,7 +100,7 @@ static inline __attribute__((always_inline))
* This routine can be called from either interrupt, task or fiber level.
* Invoked by kernel or by irq_unlock_inline()
*
* RETURNS: N/A
* @return N/A
*
* \NOMANUAL
*/
@ -124,7 +124,7 @@ static inline __attribute__((always_inline))
* at 1 from the least significant bit to 32 for the most significant bit.
* A return value of zero indicates that the value passed is zero.
*
* RETURNS: bit position from 1 to 32, or 0 if the argument is zero.
* @return bit position from 1 to 32, or 0 if the argument is zero.
*
* INTERNAL
* For Intel64 (x86_64) architectures, the 'cmovzl' can be removed
@ -175,7 +175,7 @@ static inline __attribute__((always_inline))
* at 1 from the least significant bit to 32 for the most significant bit.
* A return value of zero indicates that the value passed is zero.
*
* RETURNS: bit position from 1 to 32, or 0 if the argument is zero.
* @return bit position from 1 to 32, or 0 if the argument is zero.
*
* INTERNAL
* For Intel64 (x86_64) architectures, the 'cmovzl' can be removed
@ -254,7 +254,7 @@ static inline uint64_t _NanoTscRead(void)
*
* _do_read_cpu_timestamp - get a 32 bit CPU timestamp counter
*
* RETURNS: a 32-bit number
* @return a 32-bit number
*/
static inline inline __attribute__((always_inline))
@ -275,7 +275,7 @@ static inline inline __attribute__((always_inline))
* This function issues the 'out' instruction to write a byte to the specified
* I/O port.
*
* RETURNS: N/A
* @return N/A
*
* NOMANUAL
*/
@ -294,7 +294,7 @@ static inline inline __attribute__((always_inline))
* This function issues the 'in' instruction to read a byte from the specified
* I/O port.
*
* RETURNS: the byte read from the specified I/O port
* @return the byte read from the specified I/O port
*
* NOMANUAL
*/
@ -316,7 +316,7 @@ static inline inline __attribute__((always_inline))
* This function issues the 'out' instruction to write a word to the
* specified I/O port.
*
* RETURNS: N/A
* @return N/A
*
* NOMANUAL
*/
@ -335,7 +335,7 @@ static inline inline __attribute__((always_inline))
* This function issues the 'in' instruction to read a word from the
* specified I/O port.
*
* RETURNS: the word read from the specified I/O port
* @return the word read from the specified I/O port
*
* NOMANUAL
*/
@ -357,7 +357,7 @@ static inline inline __attribute__((always_inline))
* This function issues the 'out' instruction to write a long word to the
* specified I/O port.
*
* RETURNS: N/A
* @return N/A
*
* NOMANUAL
*/
@ -376,7 +376,7 @@ static inline inline __attribute__((always_inline))
* This function issues the 'in' instruction to read a long word from the
* specified I/O port.
*
* RETURNS: the long read from the specified I/O port
* @return the long read from the specified I/O port
*
* NOMANUAL
*/

4
include/drivers/k20_watchdog.h
View file

@ -99,7 +99,7 @@ typedef volatile struct {
* Writing 0xC520 followed by 0xD928 will unlock the write-once registers
* in the WDOG so they are writable within the WCT period.
*
* RETURNS: N/A
* @return N/A
*/
static ALWAYS_INLINE void wdog_unlock(K20_WDOG_t *wdog_p)
{
@ -130,7 +130,7 @@ static ALWAYS_INLINE void wdog_unlock(K20_WDOG_t *wdog_p)
*
* This routine will disable the watchdog timer.
*
* RETURNS: N/A
* @return N/A
*/
static ALWAYS_INLINE void wdog_disable(K20_WDOG_t *wdog_p)
{

4
kernel/microkernel/k_command_packet.c
View file

@ -73,7 +73,7 @@ uint32_t _k_test_cmd_pkt_size
*
* This routine gets the next command packet from the specified set.
*
* RETURNS: pointer to the command packet
* @return pointer to the command packet
*/
cmdPkt_t *_cmd_pkt_get(
@ -97,7 +97,7 @@ cmdPkt_t *_cmd_pkt_get(
*
* _k_task_call - send command packet to be processed by K_swapper
*
* RETURNS: N/A
* @return N/A
*/
void _k_task_call(struct k_args *cmd_packet)

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