altera_avalon_timer: new timer driver for Nios II
Tickless idle is not yet supported. We program the timer period to the desired system clock tick rate (sys_clock_hw_cycles_per_tick). This was renamed to the same name used in the Altera Embedded IP Peripherals Guide; used by other CPUs than Nios II. Change-Id: Ic4fca8c16b923295b77b63f98f45cd3483c5f560 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
Inaky Perez-Gonzalez
parent
9b3b36bd7a
commit
133dab4a63
5 changed files with 162 additions and 50 deletions
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@ -141,6 +141,7 @@ S: Supported
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F: arch/nios2/
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F: include/arch/nios2/
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F: drivers/serial/uart_altera_jtag.c
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F: drivers/timer/altera_avalon_timer.c
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NORDIC MDK
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M: Carles Cufi <carles.cufi@nordicsemi.no>
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@ -141,14 +141,15 @@ config CORTEX_M_SYSTICK
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This module implements a kernel device driver for the Cortex-M processor
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SYSTICK timer and provides the standard "system clock driver" interfaces.
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config NIOS2_AVALON_TIMER
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bool "Nios II Avalon Interval Timer"
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config ALTERA_AVALON_TIMER
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bool "Altera Avalon Interval Timer"
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default y
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depends on NIOS2
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help
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This module implements a kernel device driver for the Nios II Avalon
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Interval Timer as described in the Embedded IP documentation. It
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provides the standard "system clock driver" interfaces.
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This module implements a kernel device driver for the Altera Avalon
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Interval Timer as described in the Embedded IP documentation, for use
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with Nios II and possibly other Altera soft CPUs. It provides the
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standard "system clock driver" interfaces.
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config SYSTEM_CLOCK_DISABLE
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bool "API to disable system clock"
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@ -1,7 +1,7 @@
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obj-$(CONFIG_HPET_TIMER) += hpet.o
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obj-$(CONFIG_LOAPIC_TIMER) += loapic_timer.o
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obj-$(CONFIG_ARCV2_TIMER) += arcv2_timer0.o
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obj-$(CONFIG_NIOS2_AVALON_TIMER) += nios2_avalon_timer.o
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obj-$(CONFIG_ALTERA_AVALON_TIMER) += altera_avalon_timer.o
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_CORTEX_M_SYSTICK_AND_GDB_INFO_yy = y
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obj-$(CONFIG_CORTEX_M_SYSTICK) += cortex_m_systick.o
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154
drivers/timer/altera_avalon_timer.c
Normal file
154
drivers/timer/altera_avalon_timer.c
Normal file
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@ -0,0 +1,154 @@
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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/* STATUS register */
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#define ALTERA_AVALON_TIMER_STATUS_REG 0
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#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1)
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/* CONTROL register */
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#define ALTERA_AVALON_TIMER_CONTROL_REG 1
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1)
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#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4)
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#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3)
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/* Period and SnapShot Register for COUNTER_SIZE = 32 */
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/*----------------------------------------------------*/
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/* PERIODL register */
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#define ALTERA_AVALON_TIMER_PERIODL_REG 2
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#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODL_OFST (0)
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/* PERIODH register */
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#define ALTERA_AVALON_TIMER_PERIODH_REG 3
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#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODH_OFST (0)
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/* SNAPL register */
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#define ALTERA_AVALON_TIMER_SNAPL_REG 4
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#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPL_OFST (0)
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/* SNAPH register */
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#define ALTERA_AVALON_TIMER_SNAPH_REG 5
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#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPH_OFST (0)
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static uint32_t accumulated_cycle_count;
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static uint32_t get_snapshot(void)
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{
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#if TIMER_0_SNAPSHOT
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uint32_t snap, s1, s2;
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int key;
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key = irq_lock();
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/* Writing any data to one of the snapshot registers populates all
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* of them with the value of the counter. The data written is ignored
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*/
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_SNAPL_REG,
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1);
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s1 = _nios2_reg_read((void *)TIMER_0_BASE,
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ALTERA_AVALON_TIMER_SNAPL_REG) &
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ALTERA_AVALON_TIMER_SNAPL_MSK;
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s2 = _nios2_reg_read((void *)TIMER_0_BASE,
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ALTERA_AVALON_TIMER_SNAPH_REG) &
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ALTERA_AVALON_TIMER_SNAPH_MSK;
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irq_unlock(key);
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snap = s1 | (s2 << 16);
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return sys_clock_hw_cycles_per_tick - snap;
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#else
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return 0;
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#endif
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}
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static void timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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/* Clear the interrupt */
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_STATUS_REG,
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0);
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accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
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_sys_clock_tick_announce();
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for Avalon timer"
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#endif
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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#if TIMER_0_FIXED_PERIOD
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#error "Can't set timer period!"
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#else
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_PERIODL_REG,
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sys_clock_hw_cycles_per_tick & 0xFFFF);
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_PERIODH_REG,
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(sys_clock_hw_cycles_per_tick >> 16) & 0xFFFF);
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#endif
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IRQ_CONNECT(TIMER_0_IRQ, 0, timer_irq_handler, NULL, 0);
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irq_enable(TIMER_0_IRQ);
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/* Initial configuration: Generate interrupts, run continuously,
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* start running
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*/
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_CONTROL_REG,
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ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
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ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
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ALTERA_AVALON_TIMER_CONTROL_START_MSK);
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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uint32_t sys_cycle_get_32(void)
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{
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return accumulated_cycle_count + get_snapshot();
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}
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@ -1,44 +0,0 @@
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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/* STUB */
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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uint32_t sys_cycle_get_32(void)
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{
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/* STUB */
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return 0;
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}
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