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drivers: timer: esp32c3: add esp32c3 systimer driver to CODEOWNERS

Browse source 
Also added maintainer to the entry

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This commit is contained in:
Felipe Neves 2021-06-14 11:19:33 -03:00 • committed by Anas Nashif
commit 132ab922a8
11 changed files with 72 additions and 63 deletions
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1
CODEOWNERS
View file

@ -323,6 +323,7 @@
/drivers/timer/stm32_lptim_timer.c @FRASTM
/drivers/timer/leon_gptimer.c @martin-aberg
/drivers/timer/rcar_cmt_timer.c @julien-massot
/drivers/timer/esp32c3_sys_timer.c @uLipe
/drivers/usb/ @jfischer-no
/drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain
/drivers/video/ @loicpoulain

2
boards/riscv/esp32c3_devkitm/CMakeLists.txt
View file

@ -44,6 +44,8 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
endif()
set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
add_dependencies(app EspIdfBootloader EspPartitionTable)
board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")

2
drivers/timer/Kconfig
View file

@ -254,7 +254,7 @@ config ESP32C3_SYS_TIMER
depends on SOC_ESP32C3
default y
help
This option enables the system timer driver for the Espressif ESP32C3
This option enables the system timer driver for the Espressif ESP32C3
and provides the standard "system clock driver" interface.
config XTENSA_TIMER_ID

44
drivers/timer/esp32c3_sys_timer.c
View file

@ -21,44 +21,46 @@
static void sys_timer_isr(const void *arg)
{
ARG_UNUSED(arg);
systimer_ll_clear_alarm_int(SYSTIMER_ALARM_0);
sys_clock_announce(1);
ARG_UNUSED(arg);
systimer_ll_clear_alarm_int(SYSTIMER_ALARM_0);
sys_clock_announce(1);
}
int sys_clock_driver_init(const struct device *dev)
{
ARG_UNUSED(dev);
ARG_UNUSED(dev);
esp32c3_rom_intr_matrix_set(0, ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, SYS_TIMER_CPU_IRQ);
IRQ_CONNECT(SYS_TIMER_CPU_IRQ, 0, sys_timer_isr, NULL, 0);
irq_enable(SYS_TIMER_CPU_IRQ);
esp32c3_rom_intr_matrix_set(0,
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,
SYS_TIMER_CPU_IRQ);
IRQ_CONNECT(SYS_TIMER_CPU_IRQ, 0, sys_timer_isr, NULL, 0);
irq_enable(SYS_TIMER_CPU_IRQ);
systimer_hal_init();
systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_0, SYSTIMER_COUNTER_1);
systimer_hal_enable_counter(SYSTIMER_COUNTER_1);
systimer_hal_counter_can_stall_by_cpu(SYSTIMER_COUNTER_1, 0, true);
systimer_hal_set_alarm_period(SYSTIMER_ALARM_0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC);
systimer_hal_select_alarm_mode(SYSTIMER_ALARM_0, SYSTIMER_ALARM_MODE_PERIOD);
systimer_hal_enable_alarm_int(SYSTIMER_ALARM_0);
systimer_hal_init();
systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_0, SYSTIMER_COUNTER_1);
systimer_hal_enable_counter(SYSTIMER_COUNTER_1);
systimer_hal_counter_can_stall_by_cpu(SYSTIMER_COUNTER_1, 0, true);
systimer_hal_set_alarm_period(SYSTIMER_ALARM_0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC);
systimer_hal_select_alarm_mode(SYSTIMER_ALARM_0, SYSTIMER_ALARM_MODE_PERIOD);
systimer_hal_enable_alarm_int(SYSTIMER_ALARM_0);
return 0;
return 0;
}
void sys_clock_set_timeout(int32_t ticks, bool idle)
{
ARG_UNUSED(idle);
ARG_UNUSED(ticks);
ARG_UNUSED(idle);
ARG_UNUSED(ticks);
}
uint32_t sys_clock_elapsed(void)
{
/* Tickless is not supported yet */
return 0;
/* Tickless is not supported yet */
return 0;
}
uint32_t sys_clock_cycle_get_32(void)
{
return systimer_ll_get_counter_value_low(SYSTIMER_COUNTER_1);
return systimer_ll_get_counter_value_low(SYSTIMER_COUNTER_1);
}

2
dts/riscv/espressif/esp32c3.dtsi
View file

@ -22,7 +22,7 @@
#size-cells = <1>;
compatible = "simple-bus";
ranges;
sram0: memory@3fc7c000 {
compatible = "mmio-sram";
reg = <0x3fc7c000 0x50000>;

8
scripts/west_commands/runners/esp32.py
View file

@ -24,7 +24,7 @@ class Esp32BinaryRunner(ZephyrBinaryRunner):
self.device = device
self.boot_address = boot_address
self.part_table_address = part_table_address
self.app_address = app_address
self.app_address = app_address
self.baud = baud
self.flash_size = flash_size
self.flash_freq = flash_freq
@ -81,9 +81,9 @@ class Esp32BinaryRunner(ZephyrBinaryRunner):
'esptool', 'esptool.py')
return Esp32BinaryRunner(
cfg, args.esp_device, boot_address=args.esp_boot_address,
cfg, args.esp_device, boot_address=args.esp_boot_address,
part_table_address=args.esp_partition_table_address,
app_address=args.esp_app_address,baud=args.esp_baud_rate,
app_address=args.esp_app_address,baud=args.esp_baud_rate,
flash_size=args.esp_flash_size, flash_freq=args.esp_flash_freq,
flash_mode=args.esp_flash_mode, espidf=espidf,
bootloader_bin=args.esp_flash_bootloader,
@ -107,7 +107,7 @@ class Esp32BinaryRunner(ZephyrBinaryRunner):
cmd_flash.extend([self.boot_address, self.bootloader_bin])
cmd_flash.extend([self.part_table_address, self.partition_table_bin])
cmd_flash.extend([self.app_address, bin_name])
else :
else :
cmd_flash.extend([self.boot_address, bin_name])
self.logger.info("Flashing esp32 chip on {} ({}bps)".

14
soc/riscv/esp32c3/Kconfig.defconfig
View file

@ -6,24 +6,24 @@
if SOC_ESP32C3
config SOC
default "esp32c3"
default "esp32c3"
config NUM_IRQS
default 32
default 32
config GEN_ISR_TABLES
default y
default y
config GEN_SW_ISR_TABLE
default y
default y
config GEN_IRQ_VECTOR_TABLE
default n
default n
config XIP
default n
default n
config ISR_STACK_SIZE
default 2048
default 2048
endif

24
soc/riscv/esp32c3/Kconfig.soc
View file

@ -2,21 +2,21 @@
# SPDX-License-Identifier: Apache-2.0
config SOC_ESP32C3
bool "ESP32C3"
select RISCV
select RISCV_SOC_INIT_GP_VALUE
bool "ESP32C3"
select RISCV
select RISCV_SOC_INIT_GP_VALUE
config IDF_TARGET_ESP32C3
bool "ESP32C3 as target board"
default y
depends on SOC_ESP32C3
bool "ESP32C3 as target board"
default y
depends on SOC_ESP32C3
config ESPTOOLPY_FLASHFREQ_80M
bool
default y
depends on SOC_ESP32C3
bool
default y
depends on SOC_ESP32C3
config BOOTLOADER_ESP_IDF
bool "Use esp-idf 2nd stage bootloader"
default y
depends on SOC_ESP32C3
bool "Use esp-idf 2nd stage bootloader"
default y
depends on SOC_ESP32C3

2
soc/riscv/esp32c3/linker.ld
View file

@ -302,7 +302,7 @@ SECTIONS
*(.rodata.*)
_thread_local_end = ABSOLUTE(.);
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN(4);
. = ALIGN(4);
} GROUP_LINK_IN(ROMABLE_REGION)
#include <linker/common-rom.ld>

34
soc/riscv/esp32c3/soc.c
View file

@ -38,16 +38,16 @@ void __attribute__((section(".iram1"))) __start(void)
extern uint32_t _bss_end;
/* Configure the global pointer register
* (This should be the first thing startup does, as any other piece of code could be
* relaxed by the linker to access something relative to __global_pointer$)
* (This should be the first thing startup does, as any other piece of code could be
* relaxed by the linker to access something relative to __global_pointer$)
*/
__asm__ __volatile__(".option push\n"
".option norelax\n"
"la gp, __global_pointer$\n"
".option pop");
".option norelax\n"
"la gp, __global_pointer$\n"
".option pop");
__asm__ __volatile__("la t0, _esp32c3_vector_table \n"
"csrw mtvec, t0 \n");
__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
"csrw mtvec, t0\n");
/* Disable normal interrupts. */
csr_read_clear(mstatus, MSTATUS_MIE);
@ -84,14 +84,18 @@ void __attribute__((section(".iram1"))) __start(void)
#endif
/* Configure the Cache MMU size for instruction and rodata in flash. */
extern uint32_t esp32c3_rom_cache_set_idrom_mmu_size(uint32_t irom_size, uint32_t drom_size);
extern uint32_t esp32c3_rom_cache_set_idrom_mmu_size(uint32_t irom_size,
uint32_t drom_size);
extern int _rodata_reserved_start;
uint32_t rodata_reserved_start_align =
(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
uint32_t cache_mmu_irom_size =
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
sizeof(uint32_t);
esp32c3_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
esp32c3_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
/* set global esp32c3's INTC masking level */
esprv_intc_int_set_threshold(1);
@ -133,16 +137,16 @@ void IRAM_ATTR esp_restart_noos(void)
/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
/* Reset timer/spi/uart */
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
/* Reset dma */
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);

2
soc/riscv/esp32c3/vectors.S
View file

@ -1,4 +1,4 @@
/* Copyright 2020 Espressif Systems (Shanghai) PTE LTD
/* Copyright 2020 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/