drivers: timer: esp32c3: add esp32c3 systimer driver to CODEOWNERS
Also added maintainer to the entry Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com> Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This commit is contained in:
Felipe Neves
Anas Nashif
parent
c23b46a78a
commit
132ab922a8
11 changed files with 72 additions and 63 deletions
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@ -323,6 +323,7 @@
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/drivers/timer/stm32_lptim_timer.c @FRASTM
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/drivers/timer/leon_gptimer.c @martin-aberg
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/drivers/timer/rcar_cmt_timer.c @julien-massot
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/drivers/timer/esp32c3_sys_timer.c @uLipe
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/drivers/usb/ @jfischer-no
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/drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain
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/drivers/video/ @loicpoulain
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@ -44,6 +44,8 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
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${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
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endif()
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set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
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add_dependencies(app EspIdfBootloader EspPartitionTable)
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board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin")
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@ -21,44 +21,46 @@
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static void sys_timer_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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systimer_ll_clear_alarm_int(SYSTIMER_ALARM_0);
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sys_clock_announce(1);
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ARG_UNUSED(arg);
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systimer_ll_clear_alarm_int(SYSTIMER_ALARM_0);
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sys_clock_announce(1);
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}
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int sys_clock_driver_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(dev);
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esp32c3_rom_intr_matrix_set(0, ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, SYS_TIMER_CPU_IRQ);
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IRQ_CONNECT(SYS_TIMER_CPU_IRQ, 0, sys_timer_isr, NULL, 0);
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irq_enable(SYS_TIMER_CPU_IRQ);
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esp32c3_rom_intr_matrix_set(0,
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ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,
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SYS_TIMER_CPU_IRQ);
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IRQ_CONNECT(SYS_TIMER_CPU_IRQ, 0, sys_timer_isr, NULL, 0);
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irq_enable(SYS_TIMER_CPU_IRQ);
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systimer_hal_init();
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systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_0, SYSTIMER_COUNTER_1);
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systimer_hal_enable_counter(SYSTIMER_COUNTER_1);
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systimer_hal_counter_can_stall_by_cpu(SYSTIMER_COUNTER_1, 0, true);
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systimer_hal_set_alarm_period(SYSTIMER_ALARM_0,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC);
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systimer_hal_select_alarm_mode(SYSTIMER_ALARM_0, SYSTIMER_ALARM_MODE_PERIOD);
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systimer_hal_enable_alarm_int(SYSTIMER_ALARM_0);
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systimer_hal_init();
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systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_0, SYSTIMER_COUNTER_1);
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systimer_hal_enable_counter(SYSTIMER_COUNTER_1);
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systimer_hal_counter_can_stall_by_cpu(SYSTIMER_COUNTER_1, 0, true);
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systimer_hal_set_alarm_period(SYSTIMER_ALARM_0,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC);
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systimer_hal_select_alarm_mode(SYSTIMER_ALARM_0, SYSTIMER_ALARM_MODE_PERIOD);
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systimer_hal_enable_alarm_int(SYSTIMER_ALARM_0);
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return 0;
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return 0;
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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ARG_UNUSED(ticks);
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ARG_UNUSED(idle);
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ARG_UNUSED(ticks);
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}
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uint32_t sys_clock_elapsed(void)
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{
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/* Tickless is not supported yet */
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return 0;
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/* Tickless is not supported yet */
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return 0;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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return systimer_ll_get_counter_value_low(SYSTIMER_COUNTER_1);
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return systimer_ll_get_counter_value_low(SYSTIMER_COUNTER_1);
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}
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@ -6,24 +6,24 @@
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if SOC_ESP32C3
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config SOC
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default "esp32c3"
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default "esp32c3"
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config NUM_IRQS
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default 32
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default 32
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config GEN_ISR_TABLES
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default y
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default y
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config GEN_SW_ISR_TABLE
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default y
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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default n
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config XIP
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default n
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default n
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config ISR_STACK_SIZE
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default 2048
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default 2048
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endif
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@ -2,21 +2,21 @@
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# SPDX-License-Identifier: Apache-2.0
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config SOC_ESP32C3
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bool "ESP32C3"
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select RISCV
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select RISCV_SOC_INIT_GP_VALUE
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bool "ESP32C3"
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select RISCV
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select RISCV_SOC_INIT_GP_VALUE
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config IDF_TARGET_ESP32C3
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bool "ESP32C3 as target board"
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default y
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depends on SOC_ESP32C3
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bool "ESP32C3 as target board"
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default y
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depends on SOC_ESP32C3
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config ESPTOOLPY_FLASHFREQ_80M
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bool
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default y
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depends on SOC_ESP32C3
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bool
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default y
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depends on SOC_ESP32C3
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config BOOTLOADER_ESP_IDF
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bool "Use esp-idf 2nd stage bootloader"
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default y
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depends on SOC_ESP32C3
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bool "Use esp-idf 2nd stage bootloader"
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default y
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depends on SOC_ESP32C3
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@ -38,16 +38,16 @@ void __attribute__((section(".iram1"))) __start(void)
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extern uint32_t _bss_end;
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/* Configure the global pointer register
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* (This should be the first thing startup does, as any other piece of code could be
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* relaxed by the linker to access something relative to __global_pointer$)
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* (This should be the first thing startup does, as any other piece of code could be
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* relaxed by the linker to access something relative to __global_pointer$)
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*/
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__asm__ __volatile__(".option push\n"
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".option norelax\n"
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"la gp, __global_pointer$\n"
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".option pop");
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".option norelax\n"
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"la gp, __global_pointer$\n"
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".option pop");
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__asm__ __volatile__("la t0, _esp32c3_vector_table \n"
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"csrw mtvec, t0 \n");
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__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
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"csrw mtvec, t0\n");
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/* Disable normal interrupts. */
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csr_read_clear(mstatus, MSTATUS_MIE);
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@ -84,14 +84,18 @@ void __attribute__((section(".iram1"))) __start(void)
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#endif
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/* Configure the Cache MMU size for instruction and rodata in flash. */
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extern uint32_t esp32c3_rom_cache_set_idrom_mmu_size(uint32_t irom_size, uint32_t drom_size);
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extern uint32_t esp32c3_rom_cache_set_idrom_mmu_size(uint32_t irom_size,
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uint32_t drom_size);
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extern int _rodata_reserved_start;
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uint32_t rodata_reserved_start_align =
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(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
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uint32_t cache_mmu_irom_size =
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((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
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((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
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sizeof(uint32_t);
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esp32c3_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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esp32c3_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
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CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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/* set global esp32c3's INTC masking level */
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esprv_intc_int_set_threshold(1);
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@ -133,16 +137,16 @@ void IRAM_ATTR esp_restart_noos(void)
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/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
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SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
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SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
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SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
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SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
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BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
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SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
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SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
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SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
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BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
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REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
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/* Reset timer/spi/uart */
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
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SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
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SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
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/* Reset dma */
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
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