arm64: cache: refine arch_dcache_range()
Moved all assembly code to c code. Fixed arch_dcache_line_size_get() to get dcache line size by using "4 << dminline" and don't consider CWG according to sample code in cotexta-v8 programer guider. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
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3 changed files with 44 additions and 76 deletions
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@ -27,7 +27,6 @@ zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
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zephyr_library_sources_ifdef(CONFIG_HAS_ARM_SMCCC smccc-call.S)
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zephyr_library_sources_ifdef(CONFIG_AARCH64_IMAGE_HEADER header.S)
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zephyr_library_sources_ifdef(CONFIG_CACHE_MANAGEMENT cache.S)
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zephyr_library_sources_ifdef(CONFIG_CACHE_MANAGEMENT cache.c)
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if ((CONFIG_MP_NUM_CPUS GREATER 1) OR (CONFIG_SMP))
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zephyr_library_sources(smp.c)
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@ -1,49 +0,0 @@
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* ARM64 Cortex-A Cache management
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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.macro dcache_range_op, dcache op
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/* Calculate dcache line size */
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mrs x3, ctr_el0
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mov x2, #4
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ubfm x3, x3, #16, #19
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lsl x2, x2, x3
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/*
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* x2 = cacheline_size
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* x1 = start + end
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* x3 = cacheline_size - 1
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* x0 = x0 & ~(x3)
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*/
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add x1, x0, x1
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sub x3, x2, #1
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bic x0, x0, x3
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1:
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\dcache \op, x0
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add x0, x0, x2
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cmp x0, x1
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blo 1b
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dsb sy
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.endm
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GTEXT(arch_dcache_flush)
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SECTION_FUNC(TEXT, arch_dcache_flush)
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dcache_range_op dc civac
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ret
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GTEXT(arch_dcache_invd)
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SECTION_FUNC(TEXT, arch_dcache_invd)
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dcache_range_op dc ivac
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ret
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@ -1,7 +1,7 @@
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/* cache.c - d-cache support for AARCH64 CPUs */
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/*
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* Copyright 2020 NXP
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* Copyright 2020-2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -15,10 +15,10 @@
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#include <cache.h>
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#define CTR_EL0_DMINLINE_SHIFT 16
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#define CTR_EL0_DMINLINE_MASK GENMASK(19, 16)
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#define CTR_EL0_CWG_SHIFT 24
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#define CTR_EL0_CWG_MASK GENMASK(27, 24)
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#define CTR_EL0_DMINLINE_SHIFT 16
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#define CTR_EL0_DMINLINE_MASK BIT_MASK(4)
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#define CTR_EL0_CWG_SHIFT 24
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#define CTR_EL0_CWG_MASK BIT_MASK(4)
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/* clidr_el1 */
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#define CLIDR_EL1_LOC_SHIFT 24
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@ -39,28 +39,11 @@
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__asm__ volatile ("dc " op ", %0" :: "r" (val) : "memory"); \
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})
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int arch_dcache_flush(void *addr, size_t size);
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int arch_dcache_invd(void *addr, size_t size);
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static size_t dcache_line_size;
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int arch_dcache_range(void *addr, size_t size, int op)
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{
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if (op == K_CACHE_INVD) {
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arch_dcache_invd(addr, size);
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} else if (op == K_CACHE_WB_INVD) {
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arch_dcache_flush(addr, size);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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size_t arch_dcache_line_size_get(void)
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{
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uint64_t ctr_el0;
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uint32_t cwg;
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uint32_t dminline;
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if (dcache_line_size)
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@ -68,15 +51,50 @@ size_t arch_dcache_line_size_get(void)
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ctr_el0 = read_sysreg(CTR_EL0);
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cwg = (ctr_el0 & CTR_EL0_CWG_MASK) >> CTR_EL0_CWG_SHIFT;
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dminline = (ctr_el0 & CTR_EL0_DMINLINE_MASK) >>
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CTR_EL0_DMINLINE_SHIFT;
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dminline = (ctr_el0 >> CTR_EL0_DMINLINE_SHIFT) & CTR_EL0_DMINLINE_MASK;
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dcache_line_size = cwg ? 4 << cwg : 4 << dminline;
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dcache_line_size = 4 << dminline;
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return dcache_line_size;
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}
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/*
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* operation for data cache by virtual address to PoC
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* ops: K_CACHE_INVD: invalidate
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* K_CACHE_WB: clean
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* K_CACHE_WB_INVD: clean and invalidate
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*/
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int arch_dcache_range(void *addr, size_t size, int op)
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{
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size_t line_size;
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uintptr_t start_addr = (uintptr_t)addr;
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uintptr_t end_addr = start_addr + size;
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if (op != K_CACHE_INVD && op != K_CACHE_WB && op != K_CACHE_WB_INVD)
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return -ENOTSUP;
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line_size = arch_dcache_line_size_get();
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/* Align address to line size */
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start_addr &= ~(line_size - 1);
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do {
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if (op == K_CACHE_INVD) {
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dc_ops("ivac", start_addr);
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} else if (op == K_CACHE_WB) {
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dc_ops("cvac", start_addr);
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} else if (op == K_CACHE_WB_INVD) {
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dc_ops("civac", start_addr);
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}
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start_addr += line_size;
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} while (start_addr < end_addr);
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dsb();
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return 0;
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}
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/*
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* operation for all data cache
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* ops: K_CACHE_INVD: invalidate
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