clock: rename z_timer_cycle_get_32 -> sys_clock_cycle_get_32

This is another API that is being used in all timer drivers and is not
internal to the clock subsystem. Remove the leading z_ and make promote
it to a cross-subsystem API.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

boards/arm/qemu_cortex_m0/nrf_timer_timer.c

@@ -247,7 +247,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	k_spinlock_key_t key = k_spin_lock(&lock);
 	uint32_t ret = counter_sub(counter(), last_count) + last_count;

drivers/timer/Kconfig

@@ -30,12 +30,12 @@ config APIC_TIMER_IRQ_PRIORITY
 	  This option specifies the IRQ priority used by the local APIC timer.
 
 config APIC_TIMER_TSC
-	bool "Use invariant TSC for z_timer_cycle_get_32()"
+	bool "Use invariant TSC for sys_clock_cycle_get_32()"
 	help
 	  If your CPU supports invariant TSC, and you know the ratio of the
 	  TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC
 	  timer frequency), then enable this for a much faster and more
-	  accurate z_timer_cycle_get_32().
+	  accurate sys_clock_cycle_get_32().
 
 if APIC_TIMER_TSC
 

drivers/timer/altera_avalon_timer_hal.c

@@ -49,7 +49,7 @@ int sys_clock_driver_init(const struct device *device)
 	return 0;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	/* Per the Altera Embedded IP Peripherals guide, you cannot
 	 * use a timer instance for both the system clock and timestamps

drivers/timer/apic_timer.c

@@ -16,7 +16,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
  * This driver enables the local APIC as the Zephyr system timer. It supports
  * both legacy ("tickful") mode as well as TICKLESS_KERNEL. The driver will
  * work with any APIC that has the ARAT "always running APIC timer" feature
- * (CPUID 0x06, EAX bit 2); for the more accurate z_timer_cycle_get_32(),
+ * (CPUID 0x06, EAX bit 2); for the more accurate sys_clock_cycle_get_32(),
  * the invariant TSC feature (CPUID 0x80000007: EDX bit 8) is also required.
  * (Ultimately systems with invariant TSCs should use a TSC-based driver,
  * and the TSC-related parts should be stripped from this implementation.)
@@ -31,7 +31,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
  *     by the local APIC timer block (before it gets to the timer divider).
  *
  * CONFIG_APIC_TIMER_TSC=y enables the more accurate TSC-based cycle counter
- *     for z_timer_cycle_get_32(). This also requires the next options be set.
+ *     for sys_clock_cycle_get_32(). This also requires the next options be set.
  *
  * CONFIG_APIC_TIMER_TSC_N=<n>
  * CONFIG_APIC_TIMER_TSC_M=<m>
@@ -187,7 +187,7 @@ uint32_t sys_clock_elapsed(void)
 
 #ifdef CONFIG_APIC_TIMER_TSC
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	uint64_t tsc = z_tsc_read();
 	uint32_t cycles;
@@ -198,7 +198,7 @@ uint32_t z_timer_cycle_get_32(void)
 
 #else
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	uint32_t ret;
 	uint32_t ccr;

drivers/timer/arcv2_timer0.c

@@ -437,7 +437,7 @@ uint32_t sys_clock_elapsed(void)
 	return cyc / CYC_PER_TICK;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 #if SMP_TIMER_DRIVER
 	return z_arc_connect_gfrc_read() - start_time;

drivers/timer/arm_arch_timer.c

@@ -109,7 +109,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return (uint32_t)arm_arch_timer_count();
 }

drivers/timer/cavs_timer.c

@@ -176,7 +176,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return count32();
 }

drivers/timer/cc13x2_cc26x2_rtc_timer.c

@@ -238,7 +238,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return (AONRTCCurrent64BitValueGet() / RTC_COUNTS_PER_CYCLE)
 		& 0xFFFFFFFF;

drivers/timer/cortex_m_systick.c

@@ -238,7 +238,7 @@ uint32_t sys_clock_elapsed(void)
 	return cyc / CYC_PER_TICK;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	k_spinlock_key_t key = k_spin_lock(&lock);
 	uint32_t ret = elapsed() + cycle_count;

drivers/timer/hpet.c

@@ -204,7 +204,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return MAIN_COUNTER_REG;
 }

drivers/timer/ite_it8xxx2_timer.c

@@ -240,7 +240,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return get_timer_combine_count(CTIMER_HW_TIMER_INDEX);
 }

drivers/timer/leon_gptimer.c

@@ -86,7 +86,7 @@ uint32_t sys_clock_elapsed(void)
 	return 0;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	volatile struct gptimer_regs *regs = get_regs();
 	volatile struct gptimer_timer_regs *tmr = &regs->timer[1];

drivers/timer/litex_timer.c

@@ -39,7 +39,7 @@ static void litex_timer_irq_handler(const void *device)
 	irq_unlock(key);
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	static struct k_spinlock lock;
 	uint32_t timer_total;

drivers/timer/mchp_xec_rtos_timer.c

@@ -286,7 +286,7 @@ uint32_t sys_clock_elapsed(void)
  *    z_impl_k_busy_wait calls here. This code path uses the value as uint32_t.
  *
  */
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	uint32_t ret;
 	uint32_t ccr;

drivers/timer/native_posix_timer.c

@@ -27,7 +27,7 @@ static uint64_t last_tick_time;
  * Return the current HW cycle counter
  * (number of microseconds since boot in 32bits)
  */
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return hwm_get_time();
 }

drivers/timer/npcx_itim_timer.c

@@ -254,7 +254,7 @@ uint32_t sys_clock_elapsed(void)
 	return (uint32_t)((current - cyc_sys_announced) / SYS_CYCLES_PER_TICK);
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	k_spinlock_key_t key = k_spin_lock(&lock);
 	uint64_t current = npcx_itim_get_sys_cyc64();

drivers/timer/nrf_rtc_timer.c

@@ -393,7 +393,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	k_spinlock_key_t key = k_spin_lock(&lock);
 	uint32_t ret = counter_sub(counter(), last_count) + last_count;

drivers/timer/riscv_machine_timer.c

@@ -143,7 +143,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return (uint32_t)mtime();
 }

drivers/timer/rv32m1_lptmr_timer.c

@@ -131,7 +131,7 @@ int sys_clock_driver_init(const struct device *unused)
 	return 0;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return cycle_count + SYSTEM_TIMER_INSTANCE->CNR;
 }

drivers/timer/sam0_rtc_timer.c

@@ -310,7 +310,7 @@ uint32_t sys_clock_elapsed(void)
 #endif
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	/* Just return the absolute value of RTC cycle counter. */
 	return rtc_count();

drivers/timer/stm32_lptim_timer.c

@@ -59,7 +59,7 @@ static void lptim_irq_handler(const struct device *unused)
 		LL_LPTIM_ClearFLAG_ARRM(LPTIM1);
 
 		/* increase the total nb of autoreload count
-		 * used in the z_timer_cycle_get_32() function.
+		 * used in the sys_clock_cycle_get_32() function.
 		 * Reading the CNT register gives a reliable value
 		 */
 		uint32_t autoreload = LL_LPTIM_GetAutoReload(LPTIM1) + 1;
@@ -296,7 +296,7 @@ uint32_t sys_clock_elapsed(void)
 	return (uint32_t)(ret);
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	/* just gives the accumulated count in a number of hw cycles */
 

drivers/timer/xlnx_psttc_timer.c

@@ -189,7 +189,7 @@ uint32_t sys_clock_elapsed(void)
 #endif
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	/* Return the current counter value */
 	return read_count();

drivers/timer/xtensa_sys_timer.c

@@ -110,7 +110,7 @@ uint32_t sys_clock_elapsed(void)
 	return ret;
 }
 
-uint32_t z_timer_cycle_get_32(void)
+uint32_t sys_clock_cycle_get_32(void)
 {
 	return ccount();
 }

include/arch/arc/v2/misc.h

@@ -21,11 +21,11 @@ extern "C" {
 #ifndef _ASMLANGUAGE
 extern unsigned int z_arc_cpu_sleep_mode;
 
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 #endif
 

include/arch/arm/aarch32/misc.h

@@ -19,11 +19,11 @@ extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 static ALWAYS_INLINE void arch_nop(void)

include/arch/arm/aarch64/misc.h

@@ -20,11 +20,11 @@ extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 static ALWAYS_INLINE void arch_nop(void)

include/arch/nios2/arch.h

@@ -171,11 +171,11 @@ enum nios2_exception_cause {
 	 BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
 
 
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 static ALWAYS_INLINE void arch_nop(void)

include/arch/posix/arch.h

@@ -44,11 +44,11 @@ struct __esf {
 
 typedef struct __esf z_arch_esf_t;
 
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 static ALWAYS_INLINE void arch_nop(void)

include/arch/riscv/arch.h

@@ -347,11 +347,11 @@ static ALWAYS_INLINE void arch_nop(void)
 	__asm__ volatile("nop");
 }
 
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 #ifdef CONFIG_USERSPACE

include/arch/sparc/arch.h

@@ -92,11 +92,11 @@ static ALWAYS_INLINE void arch_nop(void)
 	__asm__ volatile ("nop");
 }
 
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 

include/arch/x86/arch.h

@@ -246,11 +246,11 @@ extern "C" {
 extern void arch_irq_enable(unsigned int irq);
 extern void arch_irq_disable(unsigned int irq);
 
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)

include/arch/xtensa/arch.h

@@ -56,11 +56,11 @@ extern void z_irq_spurious(const void *unused);
 
 #define XTENSA_ERR_NORET
 
-extern uint32_t z_timer_cycle_get_32(void);
+extern uint32_t sys_clock_cycle_get_32(void);
 
 static inline uint32_t arch_k_cycle_get_32(void)
 {
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 static ALWAYS_INLINE void arch_nop(void)

subsys/disk/disk_access_usdhc.c

@@ -718,9 +718,9 @@ enum usdhc_reset {
 
 static void usdhc_millsec_delay(unsigned int cycles_to_wait)
 {
-	unsigned int start = z_timer_cycle_get_32();
+	unsigned int start = sys_clock_cycle_get_32();
 
-	while (z_timer_cycle_get_32() - start < (cycles_to_wait * 1000))
+	while (sys_clock_cycle_get_32() - start < (cycles_to_wait * 1000))
 		;
 }
 

tests/arch/x86/info/src/timer.c

@@ -29,7 +29,7 @@ static uint32_t sync(const struct device *cmos)
 		}
 	} while (last == this);
 
-	return z_timer_cycle_get_32();
+	return sys_clock_cycle_get_32();
 }
 
 void timer(void)