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clock: rename z_timer_cycle_get_32 -> sys_clock_cycle_get_32

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This is another API that is being used in all timer drivers and is not
internal to the clock subsystem. Remove the leading z_ and make promote
it to a cross-subsystem API.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2021-03-12 12:46:52 -05:00
commit 12b53d121e
34 changed files with 49 additions and 49 deletions
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8
drivers/timer/apic_timer.c
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@ -16,7 +16,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
* This driver enables the local APIC as the Zephyr system timer. It supports
* both legacy ("tickful") mode as well as TICKLESS_KERNEL. The driver will
* work with any APIC that has the ARAT "always running APIC timer" feature
* (CPUID 0x06, EAX bit 2); for the more accurate z_timer_cycle_get_32(),
* (CPUID 0x06, EAX bit 2); for the more accurate sys_clock_cycle_get_32(),
* the invariant TSC feature (CPUID 0x80000007: EDX bit 8) is also required.
* (Ultimately systems with invariant TSCs should use a TSC-based driver,
* and the TSC-related parts should be stripped from this implementation.)
@ -31,7 +31,7 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "APIC timer doesn't support SMP");
* by the local APIC timer block (before it gets to the timer divider).
*
* CONFIG_APIC_TIMER_TSC=y enables the more accurate TSC-based cycle counter
* for z_timer_cycle_get_32(). This also requires the next options be set.
* for sys_clock_cycle_get_32(). This also requires the next options be set.
*
* CONFIG_APIC_TIMER_TSC_N=<n>
* CONFIG_APIC_TIMER_TSC_M=<m>
@ -187,7 +187,7 @@ uint32_t sys_clock_elapsed(void)
#ifdef CONFIG_APIC_TIMER_TSC
uint32_t z_timer_cycle_get_32(void)
uint32_t sys_clock_cycle_get_32(void)
{
uint64_t tsc = z_tsc_read();
uint32_t cycles;
@ -198,7 +198,7 @@ uint32_t z_timer_cycle_get_32(void)
#else
uint32_t z_timer_cycle_get_32(void)
uint32_t sys_clock_cycle_get_32(void)
{
uint32_t ret;
uint32_t ccr;