soc/intel_adsp: Update cavs-fw.py loader for cAVS 2.5 devices
Add a loader script variant for Tiger Lake (cAVS 2.5) devices, which have very slightly different loading behavior from older 1.5 DSPs. This is added as a "-v25.py" script, and the original has been renamed to cavs-fw-v15.py. Note that there is no good reason except schedule pressure that these are not the same script, I just wasn't able to make a single script work compatibly in the time available. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
eca7cc7a4a
commit
12560d54c7
2 changed files with 348 additions and 1 deletions
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@ -1,7 +1,6 @@
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#!/usr/bin/env python3
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#!/usr/bin/env python3
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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# Copyright(c) 2021 Intel Corporation. All rights reserved.
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# Copyright(c) 2021 Intel Corporation. All rights reserved.
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import ctypes
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import ctypes
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import mmap
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import mmap
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import os
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import os
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348
boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v25.py
Executable file
348
boards/xtensa/intel_adsp_cavs15/tools/cavs-fw-v25.py
Executable file
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@ -0,0 +1,348 @@
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#!/usr/bin/env python3
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# SPDX-License-Identifier: Apache-2.0
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# Copyright(c) 2021 Intel Corporation. All rights reserved.
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import ctypes
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import mmap
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import os
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import struct
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import subprocess
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import sys
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import time
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import logging
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# Intel Audio DSP firmware loader. No dependencies on anything
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# outside this file beyond Python3 builtins. Pass a signed rimage
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# file as the single argument.
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logging.basicConfig()
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log = logging.getLogger("cavs-fw")
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log.setLevel(logging.INFO)
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FW_FILE = sys.argv[1]
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PAGESZ = 4096
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HUGEPAGESZ = 2 * 1024 * 1024
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HUGEPAGE_FILE = "/dev/hugepages/cavs-fw-dma.tmp"
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HDA_PPCTL__GPROCEN = 1 << 30
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HDA_SD_CTL__TRAFFIC_PRIO = 1 << 18
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HDA_SD_CTL__START = 1 << 1
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def main():
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if os.system("lsmod | grep -q snd_sof_pci") == 0:
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log.warning("The Linux snd-sof-pci kernel module is loaded. While this")
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log.warning(" loader will normally work in such circumstances, things")
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log.warning(" will get confused if the system tries to touch the hardware")
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log.warning(" simultaneously. Operation is most reliable if it is")
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log.warning(" unloaded first.")
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# Make sure hugetlbfs is mounted (not there on chromeos)
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os.system("mount | grep -q hugetlbfs ||"
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+ " (mkdir -p /dev/hugepages; "
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+ " mount -t hugetlbfs hugetlbfs /dev/hugepages)")
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with open(FW_FILE, "rb") as f:
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fw_bytes = f.read()
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(magic, sz) = struct.unpack("4sI", fw_bytes[0:8])
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if magic == b'XMan':
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log.info(f"Trimming {sz} bytes of extended manifest")
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fw_bytes = fw_bytes[sz:len(fw_bytes)]
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(hda, sd, dsp) = map_regs() # Device register mappings
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# Reset the HDA device
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log.info("Reset HDA device")
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hda.GCTL = 0
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while hda.GCTL & 1: pass
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hda.GCTL = 1
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while not hda.GCTL & 1: pass
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# Turn on HDA "global processing enable" first. As documented,
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# this enables the audio DSP (vs. hardware HDA emulation). But it
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# actually means "enable access to the ADSP registers in PCI BAR 4" (!)
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log.info("Enable HDA global processing")
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hda.PPCTL |= HDA_PPCTL__GPROCEN
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# Turn off the DSP CPUs (each byte of ADSPCS is a bitmask for each
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# of 1-8 DSP cores: lowest byte controls "stall", the second byte
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# engages "reset", the third controls power, and the highest byte
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# is the output state for "powered" to be read after a state
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# change. Set stall and reset, and turn off power for everything:
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log.info(f"Powering down, ADSPCS = 0x{dsp.ADSPCS:x}")
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dsp.ADSPCS = 0xffff
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while dsp.ADSPCS & 0xff000000: pass
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log.info(f"Powered down, ADSPCS = 0x{dsp.ADSPCS:x}")
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# Configure our DMA stream to transfer the firmware image
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log.info(f"Configuring DMA output stream {hda_ostream_id}...")
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(buf_list_addr, num_bufs) = setup_dma_mem(fw_bytes)
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# Reset stream
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sd.CTL = 1
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while (sd.CTL & 1) == 0: pass
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sd.CTL = 0
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while (sd.CTL & 1) == 1: pass
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sd.CTL = (1 << 20) # Set stream ID to anything non-zero
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sd.BDPU = (buf_list_addr >> 32) & 0xffffffff
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sd.BDPL = buf_list_addr & 0xffffffff
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sd.CBL = len(fw_bytes)
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sd.LVI = num_bufs - 1
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# Enable "processing" on the output stream (send DMA to the DSP
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# and not the audio output hardware)
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hda.PPCTL |= (HDA_PPCTL__GPROCEN | (1 << hda_ostream_id))
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# SPIB ("Software Position In Buffer") is an Intel HDA extension
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# that puts a transfer boundary into the stream beyond which the
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# other side will not read. The ROM wants to poll on a "buffer
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# full" bit on the other side that only works with this enabled.
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hda.SPBFCTL |= (1 << hda_ostream_id)
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hda.SD_SPIB = len(fw_bytes)
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# Power up all the cores on the DSP and wait for CPU0 to show that
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# it has power. Leave stall and reset high for now
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log.info(f"Powering up DSP core #0, ADSPCS = 0x{dsp.ADSPCS:x}")
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dsp.ADSPCS = 0x01ffff
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while (dsp.ADSPCS & 0x01000000) == 0: pass
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log.info(f"Powered up {ncores(dsp)} cores, ADSPCS = 0x{dsp.ADSPCS:x}")
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# Send the DSP an IPC message to tell the device how to boot
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# ("PURGE_FW" means "load new code") and which DMA channel to use.
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# The high bit is the "BUSY" signal bit that latches a device
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# interrupt.
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#
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# Note: with cAVS 1.8+ the ROM receives the stream argument as an index
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# within the array of output streams (and we always use the first
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# one by construction). But with 1.5 it's the HDA index, and
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# depends on the number of input streams on the device.
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stream_idx = hda_ostream_id if cavs15 else 0
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ipcval = ( (1 << 31) # BUSY bit
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| (0x01 << 24) # type = PURGE_FW
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| (1 << 14) # purge_fw = 1
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| (stream_idx << 9)) # dma_id
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log.info(f"Sending PURGW_FW IPC, HIPCR = 0x{ipcval:x}")
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dsp.HIPCI = ipcval
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# Now start CPU #0 by dropping stall and reset
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log.info(f"Starting {ncores(dsp)} cores, ADSPCS = 0x{dsp.ADSPCS:x}")
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dsp.ADSPCS = 0x01fffe # Out of reset
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time.sleep(0.1)
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dsp.ADSPCS = 0x01fefe # Un-stall
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log.info(f"Started {ncores(dsp)} cores, ADSPCS = 0x{dsp.ADSPCS:x}")
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# Experimentation shows that these steps aren't actually required,
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# the ROM just charges ahead and initializes itself correctly even
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# if we don't wait for it. Do them anyway for better visibility,
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# when requested. Potentially remove later once this code is
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# mature.
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if log.level <= logging.INFO:
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# Wait for the ROM to boot and signal it's ready. NOTE: This
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# short sleep seems to be needed; if we're banging on the
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# memory window during initial boot (before/while the window
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# control registers are configured?) the DSP hardware will
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# hang fairly reliably.
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time.sleep(0.1)
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log.info(f"Waiting for ROM init, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
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while (dsp.SRAM_FW_STATUS >> 24) != 5: pass
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log.info(f"ROM ready, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
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# Newer devices have an ACK bit we can check
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if not cavs15:
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log.info(f"Awaiting IPC acknowledgment, HIPCA 0x{dsp.HIPCA:x}")
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while not dsp.HIPCA & (1 << 31): pass
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dsp.HIPCA |= ~(1 << 31)
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# Wait for it to signal ROM_INIT_DONE
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log.info(f"Awaiting ROM init... FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
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while (dsp.SRAM_FW_STATUS & 0x00ffffff) != 1: pass
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# It's ready, uncork the stream
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log.info(f"Starting DMA, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
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sd.CTL |= HDA_SD_CTL__START
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# The ROM sets a FW_ENTERED value of 5 into the bottom 28 bit
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# "state" field of FW_STATUS on entry to the app. (Pedantry: this
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# is actually ephemeral and racy, because Zephyr is free to write
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# its own data once the app launches and we might miss it.
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# There's no standard "alive" signaling from the OS, which is
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# really what we want to wait for. So give it one second and move
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# on).
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log.info(f"Waiting for load, FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
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for _ in range(100):
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alive = dsp.SRAM_FW_STATUS & ((1 << 28) - 1) == 5
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if alive: break
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time.sleep(0.01)
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if alive:
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log.info("ROM reports firmware was entered")
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else:
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log.warning(f"Load failed? FW_STATUS = 0x{dsp.SRAM_FW_STATUS:x}")
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# Turn DMA off and reset the stream. If this doesn't happen the
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# hardware continues streaming out of our now-stale page and has
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# been observed to glitch the next boot.
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sd.CTL = 1
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time.sleep(1)
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log.info(f"ADSPCS = 0x{dsp.ADSPCS:x}")
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log.info(f"Load complete, {ncores(dsp)} cores active")
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# Count of active/running cores
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def ncores(dsp):
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return bin(dsp.ADSPCS >> 24).count("1")
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def map_regs():
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# List cribbed from kernel SOF driver. Not all tested!
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for id in ["119a", "5a98", "1a98", "3198", "9dc8",
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"a348", "34C8", "38c8", "4dc8", "02c8",
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"06c8", "a3f0", "a0c8", "4b55", "4b58"]:
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p = runx(f"grep -il PCI_ID=8086:{id} /sys/bus/pci/devices/*/uevent")
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if p:
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pcidir = os.path.dirname(p)
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break
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# Detect hardware version, this matters in a few spots
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global cavs15
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cavs15 = id in [ "5a98", "1a98", "3198" ]
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log.info(f"Detected cAVS {'1.5' if cavs15 else '1.8+'} hardware")
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# Disengage runtime power management so the kernel doesn't put it to sleep
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with open(pcidir + b"/power/control", "w") as ctrl:
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ctrl.write("on")
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# Make sure PCI memory space access and busmastering are enabled.
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# Also disable interrupts so as not to confuse the kernel.
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with open(pcidir + b"/config", "wb+") as cfg:
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cfg.seek(4)
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cfg.write(b'\x06\x04')
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time.sleep(0.1)
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hdamem = bar_map(pcidir, 0)
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# Standard HD Audio Registers
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hda = Regs(hdamem)
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hda.GCAP = 0x0000
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hda.GCTL = 0x0008
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hda.SPBFCTL = 0x0704
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hda.PPCTL = 0x0804
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# Find the ID of the first output stream
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global hda_ostream_id
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hda_ostream_id = (hda.GCAP >> 8) & 0x0f # number of input streams
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log.info(f"Selected output stream {hda_ostream_id} (GCAP = 0x{hda.GCAP:x})")
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hda.SD_SPIB = 0x0708 + (8 * hda_ostream_id)
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hda.freeze()
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# Standard HD Audio Stream Descriptor
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sd = Regs(hdamem + 0x0080 + (hda_ostream_id * 0x20))
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sd.CTL = 0x00
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sd.LPIB = 0x04
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sd.CBL = 0x08
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sd.LVI = 0x0c
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sd.FMT = 0x12
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sd.BDPL = 0x18
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sd.BDPU = 0x1c
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sd.freeze()
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# Intel Audio DSP Registers
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dsp = Regs(bar_map(pcidir, 4))
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dsp.ADSPCS = 0x00004
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if cavs15:
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dsp.HIPCI = 0x00048 # original name of the register...
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else:
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dsp.HIPCI = 0x000d0 # ...now named "HIPCR" per 1.8+ docs
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dsp.HIPCA = 0x000d4
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dsp.SRAM_FW_STATUS = 0x80000 # Start of first SRAM window
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dsp.freeze()
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return (hda, sd, dsp)
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def setup_dma_mem(fw_bytes):
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(mem, phys_addr) = map_phys_mem()
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mem[0:len(fw_bytes)] = fw_bytes
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log.info("Mapped 2M huge page at 0x%x to contain %d bytes of firmware"
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% (phys_addr, len(fw_bytes)))
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# HDA requires at least two buffers be defined, but we don't care
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# about boundaries because it's all a contiguous region. Place a
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# vestigial 128-byte (minimum size and alignment) buffer after the
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# main one, and put the 4-entry BDL list into the final 128 bytes
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# of the page.
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buf0_len = HUGEPAGESZ - 2 * 128
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buf1_len = 128
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bdl_off = buf0_len + buf1_len
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mem[bdl_off:bdl_off + 32] = struct.pack("<QQQQ",
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phys_addr, buf0_len,
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phys_addr + buf0_len, buf1_len)
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return (phys_addr + bdl_off, 2)
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global_mmaps = [] # protect mmap mappings from garbage collection!
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# Maps 2M of contiguous memory using a single page from hugetlbfs,
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# then locates its physical address for use as a DMA buffer.
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def map_phys_mem():
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# Ensure the kernel has enough budget for one new page
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free = int(runx("awk '/HugePages_Free/ {print $2}' /proc/meminfo"))
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if free == 0:
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tot = 1 + int(runx("awk '/HugePages_Total/ {print $2}' /proc/meminfo"))
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os.system(f"echo {tot} > /proc/sys/vm/nr_hugepages")
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hugef = open(HUGEPAGE_FILE, "w+")
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hugef.truncate(HUGEPAGESZ)
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mem = mmap.mmap(hugef.fileno(), HUGEPAGESZ)
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global_mmaps.append(mem)
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os.unlink(HUGEPAGE_FILE)
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# Find the local process address of the mapping, then use that to
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# extract the physical address from the kernel's pagemap
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# interface. The physical page frame number occupies the bottom
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# bits of the entry.
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mem[0] = 0 # Fault the page in so it has an address!
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vaddr = ctypes.addressof(ctypes.c_int.from_buffer(mem))
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vpagenum = vaddr >> 12
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pagemap = open("/proc/self/pagemap", "rb")
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pagemap.seek(vpagenum * 8)
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pent = pagemap.read(8)
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paddr = (struct.unpack("Q", pent)[0] & ((1 << 54) - 1)) * PAGESZ
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pagemap.close()
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return (mem, paddr)
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# Maps a PCI BAR and returns the in-process address
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def bar_map(pcidir, barnum):
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||||||
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f = open(pcidir.decode() + "/resource" + str(barnum), "r+")
|
||||||
|
mm = mmap.mmap(f.fileno(), os.fstat(f.fileno()).st_size)
|
||||||
|
global_mmaps.append(mm)
|
||||||
|
return ctypes.addressof(ctypes.c_int.from_buffer(mm))
|
||||||
|
|
||||||
|
# Syntactic sugar to make register block definition & use look nice.
|
||||||
|
# Instantiate from a base address, assign offsets to (uint32) named
|
||||||
|
# registers as fields, call freeze(), then the field acts as a direct
|
||||||
|
# alias for the register!
|
||||||
|
class Regs:
|
||||||
|
def __init__(self, base_addr):
|
||||||
|
vars(self)["base_addr"] = base_addr
|
||||||
|
vars(self)["ptrs"] = {}
|
||||||
|
vars(self)["frozen"] = False
|
||||||
|
def freeze(self):
|
||||||
|
vars(self)["frozen"] = True
|
||||||
|
def __setattr__(self, name, val):
|
||||||
|
if not self.frozen and name not in self.ptrs:
|
||||||
|
addr = self.base_addr + val
|
||||||
|
self.ptrs[name] = ctypes.c_uint32.from_address(addr)
|
||||||
|
else:
|
||||||
|
self.ptrs[name].value = val
|
||||||
|
def __getattr__(self, name):
|
||||||
|
return self.ptrs[name].value
|
||||||
|
|
||||||
|
def runx(cmd):
|
||||||
|
return subprocess.Popen(["sh", "-c", cmd],
|
||||||
|
stdout=subprocess.PIPE).stdout.read()
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
||||||
Loading…
Add table
Add a link
Reference in a new issue