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boards: nordic: add nrf7002dk

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Add nrf7002dk board.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This commit is contained in:
Bjarki Arge Andreasen 2024-07-25 09:51:29 +02:00 • committed by Anas Nashif
commit 12559fe6fc
32 changed files with 1422 additions and 0 deletions
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11
boards/nordic/nrf7002dk/CMakeLists.txt Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if((CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP OR
CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR
CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 OR
CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS) AND
CONFIG_BOARD_ENABLE_CPUNET)
zephyr_library()
zephyr_library_sources(nrf5340_cpunet_reset.c)
endif()

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boards/nordic/nrf7002dk/Kconfig Normal file
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# nRF5340 DK board configuration
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config IPM_NRFX
default IPM
config MBOX_NRFX_IPC
default MBOX
if BOARD_NRF7002DK_NRF5340_CPUAPP || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
config BT_HCI_IPC
default y if BT
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 4096 if BT_HCI_IPC
config BOARD_ENABLE_CPUNET
bool "nRF53 Network MCU"
select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \
$(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER))
help
This option enables releasing the Network 'force off' signal, which
as a consequence will power up the Network MCU during system boot.
Additionally, the option allocates GPIO pins that will be used by UARTE
of the Network MCU.
Note: GPIO pin allocation can only be configured by the secure Application
MCU firmware, so when this option is used with the non-secure version of
the board, the application needs to take into consideration, that the
secure firmware image must already have configured GPIO allocation for the
Network MCU.
default y if (BT || NRF_802154_SER_HOST)
config DOMAIN_CPUNET_BOARD
string
default "nrf7002dk/nrf5340/cpunet"
depends on BOARD_ENABLE_CPUNET
help
The board which will be used for CPUNET domain when creating a multi
image application where one or more images should be located on
another board. For example hci_ipc on the nRF5340_cpunet for
Bluetooth applications.
endif
if BOARD_NRF7002DK_NRF5340_CPUNET
config BT_CTLR
default y if BT
config BT_ECC
default y if BT
config DOMAIN_CPUAPP_BOARD
string
default "nrf7002dk/nrf5340/cpuapp" if BOARD_NRF7002DK_NRF5340_CPUAPP
default "nrf7002dk/nrf5340/cpuapp/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NS
default "nrf7002dk/nrf5340/cpuapp/nrf7001" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001
default "nrf7002dk/nrf5340/cpuapp/nrf7001/ns" if BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
help
The board which will be used for CPUAPP domain when creating a multi
image application where one or more images should be located on
another board.
endif

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boards/nordic/nrf7002dk/Kconfig.defconfig Normal file
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# nRF5340 DK nRF5340 board configuration
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if BOARD_NRF7002DK_NRF5340_CPUAPP || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
# By default, if we build for a Non-Secure version of the board,
# force building with TF-M as the Secure Execution Environment.
config BUILD_WITH_TFM
default y if BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
if BUILD_WITH_TFM
# By default, if we build with TF-M, instruct build system to
# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
config TFM_FLASH_MERGED_BINARY
bool
default y
endif # BUILD_WITH_TFM
# Code Partition:
#
# For the secure version of the board the firmware is linked at the beginning
# of the flash, or into the code-partition defined in DT if it is intended to
# be loaded by MCUboot. If the secure firmware is to be combined with a non-
# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
# be restricted to the size of its code partition.
#
# For the non-secure version of the board, the firmware
# must be linked into the code-partition (non-secure) defined in DT, regardless.
# Apply this configuration below by setting the Kconfig symbols used by
# the linker according to the information extracted from DT partitions.
# SRAM Partition:
#
# If the secure firmware is to be combined with a non-secure image
# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always
# be restricted to the secure image SRAM partition (sram-secure-partition).
# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram
# may be used by the image.
#
# For the non-secure version of the board, the firmware image SRAM is
# always restricted to the allocated non-secure SRAM partition.
#
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
if (BOARD_NRF7002DK_NRF5340_CPUAPP || BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001) && \
TRUSTED_EXECUTION_SECURE
config FLASH_LOAD_SIZE
default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
config SRAM_SIZE
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)
endif
if BOARD_NRF7002DK_NRF5340_CPUAPP_NS || BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS
config FLASH_LOAD_OFFSET
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
config FLASH_LOAD_SIZE
default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
endif
endif

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boards/nordic/nrf7002dk/Kconfig.nrf7002dk Normal file
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# Copyright (c) 2024 Nordic Semiconductor
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF7002DK
select SOC_NRF5340_CPUNET_QKAA if BOARD_NRF7002DK_NRF5340_CPUNET
select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF7002DK_NRF5340_CPUAPP || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NS || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 || \
BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS

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boards/nordic/nrf7002dk/board.cmake Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR
CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS)
set(TFM_PUBLIC_KEY_FORMAT "full")
endif()
if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP OR
CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR
CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 OR
CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS)
board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
endif()
if(CONFIG_TFM_FLASH_MERGED_BINARY)
set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex")
endif()
if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUNET)
board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
endif()
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

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boards/nordic/nrf7002dk/board.yml Normal file
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board:
name: nrf7002dk
vendor: nordic
socs:
- name: nrf5340
variants:
- name: ns
cpucluster: cpuapp
- name: nrf7001
cpucluster: cpuapp
variants:
- name: ns

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boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf5340_cpuapp_common_pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,bt-hci = &bt_hci_ipc0;
nordic,802154-spinel-ipc = &ipc0;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_led0: pwm_led_0 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_1>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 4 0>, /* A0 */
<1 0 &gpio0 5 0>, /* A1 */
<2 0 &gpio0 6 0>, /* A2 */
<3 0 &gpio0 7 0>, /* A3 */
<4 0 &gpio0 25 0>, /* A4 */
<5 0 &gpio0 26 0>, /* A5 */
<6 0 &gpio1 0 0>, /* D0 */
<7 0 &gpio1 1 0>, /* D1 */
<8 0 &gpio1 4 0>, /* D2 */
<9 0 &gpio1 5 0>, /* D3 */
<10 0 &gpio1 6 0>, /* D4 */
<11 0 &gpio1 7 0>, /* D5 */
<12 0 &gpio1 8 0>, /* D6 */
<13 0 &gpio1 9 0>, /* D7 */
<14 0 &gpio1 10 0>, /* D8 */
<15 0 &gpio1 11 0>, /* D9 */
<16 0 &gpio1 12 0>, /* D10 */
<17 0 &gpio1 13 0>, /* D11 */
<18 0 &gpio1 14 0>, /* D12 */
<19 0 &gpio1 15 0>, /* D13 */
<20 0 &gpio1 2 0>, /* D14 */
<21 0 &gpio1 3 0>; /* D15 */
};
arduino_adc: analog-connector {
compatible = "arduino,uno-adc";
#io-channel-cells = <1>;
io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */
<1 &adc 1>, /* A1 = P0.5 = AIN1 */
<2 &adc 2>, /* A2 = P0.6 = AIN2 */
<3 &adc 3>, /* A3 = P0.7 = AIN3 */
<4 &adc 4>, /* A4 = P0.25 = AIN4 */
<5 &adc 5>; /* A5 = P0.26 = AIN5 */
};
gpio_fwd: nrf-gpio-forwarder {
compatible = "nordic,nrf-gpio-forwarder";
status = "okay";
uart {
gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio1 5 0>, <&gpio1 4 0>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
led1 = &led1;
pwm-led0 = &pwm_led0;
sw0 = &button0;
sw1 = &button1;
bootloader-led0 = &led0;
mcuboot-button0 = &button0;
mcuboot-led0 = &led0;
watchdog0 = &wdt0;
};
};
&vregmain {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&vregradio {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&vregh {
status = "okay";
};
&adc {
status = "okay";
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
arduino_i2c: &i2c1 {
compatible = "nordic,nrf-twim";
status = "okay";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
pinctrl-names = "default", "sleep";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&spi4 {
compatible = "nordic,nrf-spim";
status = "okay";
pinctrl-0 = <&spi4_default>;
pinctrl-1 = <&spi4_sleep>;
pinctrl-names = "default", "sleep";
cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
mx25r64: mx25r6435f@0 {
compatible = "jedec,spi-nor";
status = "disabled";
reg = <0>;
spi-max-frequency = <33000000>;
jedec-id = [c2 28 17];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
size = <67108864>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <5000>;
};
};
&qspi {
status = "okay";
pinctrl-0 = <&qspi_default>;
pinctrl-1 = <&qspi_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_serial: &uart1 {
compatible = "nordic,nrf-uarte";
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-1 = <&uart1_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_spi: &spi3 {
compatible = "nordic,nrf-spim";
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
pinctrl-0 = <&spi3_default>;
pinctrl-1 = <&spi3_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
};
slot0_partition: partition@10000 {
label = "image-0";
};
slot0_ns_partition: partition@50000 {
label = "image-0-nonsecure";
};
slot1_partition: partition@80000 {
label = "image-1";
};
slot1_ns_partition: partition@c0000 {
label = "image-1-nonsecure";
};
/* 0xf0000 to 0xf7fff reserved for TF-M partitions */
storage_partition: partition@f8000 {
label = "storage";
reg = <0x000f8000 0x00008000>;
};
};
};
&ieee802154 {
status = "okay";
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
/ {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram0_image: image@20000000 {
/* Zephyr image(s) memory */
};
sram0_s: image_s@20000000 {
/* Secure image memory */
};
sram0_ns: image_ns@20040000 {
/* Non-Secure image memory */
};
};
};
/* Include partition configuration file */
#include "nrf5340_cpuapp_common_partition_conf.dts"

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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Default Flash planning for nrf7002dk_nrf5340 CPUAPP (Application MCU).
*
* Zephyr build for nRF5340 with ARM TrustZone-M support,
* implies building Secure and Non-Secure Zephyr images.
*
* Secure image will be placed, by default, in flash0
* (or in slot0, if MCUboot is present).
* Secure image will use sram0 for system memory.
*
* Non-Secure image will be placed in slot0_ns, and use
* sram0_ns for system memory.
*
* Note that the Secure image only requires knowledge of
* the beginning of the Non-Secure image (not its size).
*/
&slot0_partition {
reg = <0x00010000 0x40000>;
};
&slot0_ns_partition {
reg = <0x00050000 0x30000>;
};
&slot1_partition {
reg = <0x00080000 0x40000>;
};
&slot1_ns_partition {
reg = <0x000c0000 0x30000>;
};
/* Default SRAM planning when building for nRF5340 with
* ARM TrustZone-M support
* - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
* - Middle 192 kB allocated to Non-Secure image (sram0_ns)
* - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
* (see nrf5340_shared_sram_planning_conf.dts)
*/
&sram0_image {
reg = <0x20000000 DT_SIZE_K(448)>;
};
&sram0_s {
reg = <0x20000000 DT_SIZE_K(256)>;
};
&sram0_ns {
reg = <0x20040000 DT_SIZE_K(192)>;
};
/* Include shared RAM configuration file */
#include "nrf5340_shared_sram_planning_conf.dts"

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boards/nordic/nrf7002dk/nrf5340_cpuapp_common_pinctrl.dtsi Normal file
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&pinctrl {
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
};
};
i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
low-power-enable;
};
};
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RTS, 0, 19)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_CTS, 0, 21)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_RTS, 0, 19)>,
<NRF_PSEL(UART_CTS, 0, 21)>;
low-power-enable;
};
};
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
low-power-enable;
};
};
qspi_default: qspi_default {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
<NRF_PSEL(QSPI_IO0, 0, 13)>,
<NRF_PSEL(QSPI_IO1, 0, 14)>,
<NRF_PSEL(QSPI_IO2, 0, 15)>,
<NRF_PSEL(QSPI_IO3, 0, 16)>,
<NRF_PSEL(QSPI_CSN, 0, 18)>;
};
};
qspi_sleep: qspi_sleep {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
<NRF_PSEL(QSPI_IO0, 0, 13)>,
<NRF_PSEL(QSPI_IO1, 0, 14)>,
<NRF_PSEL(QSPI_IO2, 0, 15)>,
<NRF_PSEL(QSPI_IO3, 0, 16)>,
<NRF_PSEL(QSPI_CSN, 0, 18)>;
low-power-enable;
};
};
uart1_default: uart1_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 0)>;
bias-pull-up;
};
};
uart1_sleep: uart1_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>,
<NRF_PSEL(UART_RX, 1, 0)>;
low-power-enable;
};
};
spi3_default: spi3_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
};
};
spi3_sleep: spi3_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
low-power-enable;
};
};
spi4_default: spi4_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
<NRF_PSEL(SPIM_MISO, 0, 10)>,
<NRF_PSEL(SPIM_MOSI, 0, 9)>;
};
};
spi4_sleep: spi4_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
<NRF_PSEL(SPIM_MISO, 0, 10)>,
<NRF_PSEL(SPIM_MOSI, 0, 9)>;
low-power-enable;
};
};
};

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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/sys/util_macro.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <hal/nrf_reset.h>
LOG_MODULE_REGISTER(nrf7002dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL);
#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP)
#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h>
#endif
static void remoteproc_mgr_config(void)
{
#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) && \
(!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM))
/* Route Bluetooth Controller Debug Pins */
DEBUG_SETUP();
#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */
#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
/* Retain nRF5340 Network MCU in Secure domain (bus
* accesses by Network MCU will have Secure attribute set).
*/
NRF_SPU->EXTDOMAIN[0].PERM = BIT(4);
#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */
}
static int remoteproc_mgr_boot(void)
{
/* Secure domain may configure permissions for the Network MCU. */
remoteproc_mgr_config();
#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE)
/*
* Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies
* building also a Non-Secure image. The Non-Secure image will, in
* this case do the remainder of actions to properly configure and
* boot the Network MCU.
*/
/* Release the Network MCU, 'Release force off signal' */
nrf_reset_network_force_off(NRF_RESET, false);
LOG_DBG("Network MCU released.");
#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */
return 0;
}
SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);

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boards/nordic/nrf7002dk/nrf5340_shared_sram_planning_conf.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Default shared SRAM planning when building for nRF5340.
* This file is included by both nRF5340 CPUAPP (Application MCU)
* and nRF5340 CPUNET (Network MCU).
* - 64 kB SRAM allocated as Shared memory (sram0_shared)
* - Region defined after the image SRAM of Application MCU
*/
/ {
chosen {
/* shared memory reserved for the inter-processor communication */
zephyr,ipc_shm = &sram0_shared;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram0_shared: memory@20070000 {
/* SRAM allocated to shared memory */
reg = <0x20070000 0x10000>;
};
};
};

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boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "nrf5340_cpuapp_common.dtsi"
#include "nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi"
/ {
model = "Nordic NRF7002 DK NRF5340 Application";
compatible = "nordic,nrf7002-dk-nrf5340-cpuapp";
chosen {
zephyr,sram = &sram0_image;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,sram-secure-partition = &sram0_s;
zephyr,sram-non-secure-partition = &sram0_ns;
zephyr,wifi = &wlan0;
};
};
&qspi {
nrf70: nrf7002@1 {
compatible = "nordic,nrf7002-qspi";
status = "okay";
reg = <1>;
qspi-frequency = <24000000>;
qspi-quad-mode;
#include "nrf70_common.dtsi"
#include "nrf70_common_coex.dtsi"
#include "nrf70_common_5g.dtsi"
};
};

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boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml Normal file
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identifier: nrf7002dk/nrf5340/cpuapp
name: NRF7002-DK-NRF5340-application-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 448
flash: 1024
supported:
- gpio
- i2c
- i2s
- pwm
- watchdog
- usbd
- usb_device
- netif:openthread
vendor: nordic

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boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig Normal file
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# SPDX-License-Identifier: Apache-2.0
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_ARM_TRUSTZONE_M=y
# Enable GPIO
CONFIG_GPIO=y
# Enable PINCTRL
CONFIG_PINCTRL=y
# Enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

37
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "nrf5340_cpuapp_common.dtsi"
#include "nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi"
/ {
model = "Nordic NRF7002 DK NRF5340 Application";
compatible = "nordic,nrf7002-dk-nrf5340-cpuapp";
chosen {
zephyr,sram = &sram0_image;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,sram-secure-partition = &sram0_s;
zephyr,sram-non-secure-partition = &sram0_ns;
zephyr,wifi = &wlan0;
};
};
&qspi {
nrf70: nrf7001@1 {
compatible = "nordic,nrf7001-qspi";
status = "okay";
reg = <1>;
qspi-frequency = <24000000>;
qspi-quad-mode;
#include "nrf70_common.dtsi"
#include "nrf70_common_coex.dtsi"
};
};

20
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml Normal file
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identifier: nrf7002dk/nrf5340/cpuapp/nrf7001
name: NRF7002-DK-NRF7001-NRF5340-application-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 448
flash: 1024
supported:
- gpio
- i2c
- i2s
- pwm
- watchdog
- usbd
- usb_device
- netif:openthread
vendor: nordic

24
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_ARM_TRUSTZONE_M=y
# enable GPIO
CONFIG_GPIO=y
# enable PINCTRL
CONFIG_PINCTRL=y
# Enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

40
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
#include "nrf5340_cpuapp_common.dtsi"
/ {
model = "Nordic NRF5340 DK NRF5340 Application";
compatible = "nordic,nrf5340-dk-nrf5340-cpuapp";
chosen {
zephyr,sram = &sram0_ns;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_ns_partition;
zephyr,entropy = &psa_rng;
zephyr,wifi = &wlan0;
};
psa_rng: psa-rng {
compatible = "zephyr,psa-crypto-rng";
status = "okay";
};
};
&qspi {
nrf70: nrf7001@1 {
compatible = "nordic,nrf7001-qspi";
status = "okay";
reg = <1>;
qspi-frequency = <24000000>;
qspi-quad-mode;
#include "nrf70_common.dtsi"
#include "nrf70_common_coex.dtsi"
};
};

19
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns.yaml Normal file
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identifier: nrf7002dk/nrf5340/cpuapp/nrf7001/ns
name: NRF7002-DK-NRF7001-NRF5340-application-MCU-Non-Secure
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 192
flash: 192
supported:
- gpio
- i2c
- pwm
- watchdog
- usbd
- usb_device
- netif:openthread
vendor: nordic

27
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_ns_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_ARM_TRUSTZONE_M=y
# This Board implies building Non-Secure firmware
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
# enable GPIO
CONFIG_GPIO=y
# enable PINCTRL
CONFIG_PINCTRL=y
# Enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

41
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
#include "nrf5340_cpuapp_common.dtsi"
/ {
model = "Nordic NRF5340 DK NRF5340 Application";
compatible = "nordic,nrf5340-dk-nrf5340-cpuapp";
chosen {
zephyr,sram = &sram0_ns;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_ns_partition;
zephyr,entropy = &psa_rng;
zephyr,wifi = &wlan0;
};
psa_rng: psa-rng {
compatible = "zephyr,psa-crypto-rng";
status = "okay";
};
};
&qspi {
nrf70: nrf7002@1 {
compatible = "nordic,nrf7002-qspi";
status = "okay";
reg = <1>;
qspi-frequency = <24000000>;
qspi-quad-mode;
#include "nrf70_common.dtsi"
#include "nrf70_common_coex.dtsi"
#include "nrf70_common_5g.dtsi"
};
};

19
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns.yaml Normal file
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identifier: nrf7002dk/nrf5340/cpuapp/ns
name: NRF7002-DK-NRF5340-application-MCU-Non-Secure
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 192
flash: 192
supported:
- gpio
- i2c
- pwm
- watchdog
- usbd
- usb_device
- netif:openthread
vendor: nordic

26
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_ns_defconfig Normal file
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# SPDX-License-Identifier: Apache-2.0
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_ARM_TRUSTZONE_M=y
# This Board implies building Non-Secure firmware
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
# enable GPIO
CONFIG_GPIO=y
# enable PINCTRL
CONFIG_PINCTRL=y
# Enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

18
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_pinctrl.dtsi Normal file
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&pinctrl {
spi2_default: spi2_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
};
};
spi2_sleep: spi2_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
low-power-enable;
};
};
};

176
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf5340_cpunet_qkaa.dtsi>
#include "nrf7002dk_nrf5340_cpunet_pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Nordic NRF7002 DK NRF5340 Network";
compatible = "nordic,nrf7002-dk-nrf5340-cpunet";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,bt-hci-ipc = &ipc0;
nordic,802154-spinel-ipc = &ipc0;
zephyr,sram = &sram1;
zephyr,flash = &flash1;
zephyr,code-partition = &slot0_partition;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_1>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 4 0>, /* A0 */
<1 0 &gpio0 5 0>, /* A1 */
<2 0 &gpio0 6 0>, /* A2 */
<3 0 &gpio0 7 0>, /* A3 */
<4 0 &gpio0 25 0>, /* A4 */
<5 0 &gpio0 26 0>, /* A5 */
<6 0 &gpio1 0 0>, /* D0 */
<7 0 &gpio1 1 0>, /* D1 */
<8 0 &gpio1 4 0>, /* D2 */
<9 0 &gpio1 5 0>, /* D3 */
<10 0 &gpio1 6 0>, /* D4 */
<11 0 &gpio1 7 0>, /* D5 */
<12 0 &gpio1 8 0>, /* D6 */
<13 0 &gpio1 9 0>, /* D7 */
<14 0 &gpio1 10 0>, /* D8 */
<15 0 &gpio1 11 0>, /* D9 */
<16 0 &gpio1 12 0>, /* D10 */
<17 0 &gpio1 13 0>, /* D11 */
<18 0 &gpio1 14 0>, /* D12 */
<19 0 &gpio1 15 0>, /* D13 */
<20 0 &gpio1 2 0>, /* D14 */
<21 0 &gpio1 3 0>; /* D15 */
};
nrf70: coex {
status = "okay";
compatible = "nordic,nrf70-coex";
#include "nrf70_common_coex.dtsi"
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
led1 = &led1;
sw0 = &button0;
sw1 = &button1;
bootloader-led0 = &led0;
mcuboot-button0 = &button0;
mcuboot-led0 = &led0;
watchdog0 = &wdt0;
};
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_serial: &uart0{};
arduino_i2c: &i2c0 {
compatible = "nordic,nrf-twim";
/* Cannot be used together with uart0. */
/* status = "okay"; */
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_spi: &spi0 {
compatible = "nordic,nrf-spim";
/* Cannot be used together with uart0. */
/* status = "okay"; */
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
pinctrl-0 = <&spi0_default>;
pinctrl-1 = <&spi0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash1 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x17000>;
};
slot1_partition: partition@23000 {
label = "image-1";
reg = <0x00023000 0x17000>;
};
storage_partition: partition@3a000 {
label = "storage";
reg = <0x0003a000 0x6000>;
};
};
};
&ieee802154 {
status = "okay";
};
/* Include shared RAM configuration file */
#include "nrf5340_shared_sram_planning_conf.dts"

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boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml Normal file
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identifier: nrf7002dk/nrf5340/cpunet
name: NRF7002-DK-NRF5340-network-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 64
flash: 256
supported:
- gpio
- watchdog
vendor: nordic

20
boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig Normal file
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# SPDX-License-Identifier: Apache-2.0
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
# enable PINCTRL
CONFIG_PINCTRL=y
# Enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

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boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_pinctrl.dtsi Normal file
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&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>,
<NRF_PSEL(UART_RTS, 1, 5)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 0)>,
<NRF_PSEL(UART_CTS, 1, 4)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>,
<NRF_PSEL(UART_RX, 1, 0)>,
<NRF_PSEL(UART_RTS, 1, 5)>,
<NRF_PSEL(UART_CTS, 1, 4)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
low-power-enable;
};
};
spi0_default: spi0_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
};
};
spi0_sleep: spi0_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
low-power-enable;
};
};
};

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boards/nordic/nrf7002dk/nrf70_common.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
iovdd-ctrl-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
bucken-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
host-irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
wifi-max-tx-pwr-2g-dsss = <21>;
wifi-max-tx-pwr-2g-mcs0 = <16>;
wifi-max-tx-pwr-2g-mcs7 = <16>;
wlan0: wlan {
compatible = "nordic,wlan";
};

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boards/nordic/nrf7002dk/nrf70_common_5g.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
wifi-max-tx-pwr-5g-low-mcs0 = <9>;
wifi-max-tx-pwr-5g-low-mcs7 = <9>;
wifi-max-tx-pwr-5g-mid-mcs0 = <11>;
wifi-max-tx-pwr-5g-mid-mcs7 = <11>;
wifi-max-tx-pwr-5g-high-mcs0 = <13>;
wifi-max-tx-pwr-5g-high-mcs7 = <13>;

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boards/nordic/nrf7002dk/nrf70_common_coex.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
srrf-switch-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;

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boards/nordic/nrf7002dk/pre_dt_board.cmake Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - flash-controller@39000 & kmu@39000
# - power@5000 & clock@5000
# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")