drivers: dma: Introduce support for SiWx91x
Implement DMA driver for siwx917 using UDMA peripheral. For now, Scatter/Gather DMA is not yet supported. Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This commit is contained in:
Jérôme Pouiller
Benjamin Cabé
parent
300f4fe3f4
commit
124c79dd23
6 changed files with 475 additions and 0 deletions
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@ -41,6 +41,7 @@ zephyr_library_sources_ifdef(CONFIG_DMA_INFINEON_CAT1 dma_ifx_cat1.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_SEDI dma_sedi.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_SI32 dma_si32.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_SILABS_LDMA dma_silabs_ldma.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_SILABS_SIWX91X dma_silabs_siwx91x.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_SMARTBOND dma_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_NXP_SOF_HOST_DMA dma_nxp_sof_host_dma.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_EMUL dma_emul.c)
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@ -76,6 +76,8 @@ source "drivers/dma/Kconfig.si32"
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source "drivers/dma/Kconfig.silabs"
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source "drivers/dma/Kconfig.siwx91x"
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source "drivers/dma/Kconfig.smartbond"
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source "drivers/dma/Kconfig.nxp_sof_host_dma"
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9
drivers/dma/Kconfig.siwx91x
Normal file
9
drivers/dma/Kconfig.siwx91x
Normal file
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@ -0,0 +1,9 @@
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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config DMA_SILABS_SIWX91X
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bool "Silabs SiWx91x DMA driver"
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default y
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depends on DT_HAS_SILABS_SIWX91X_DMA_ENABLED
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help
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Enable the High Power(HP)/Ultra Low Power(ULP) DMA driver for the Silabs SiWx91x SoC series.
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429
drivers/dma/dma_silabs_siwx91x.c
Normal file
429
drivers/dma/dma_silabs_siwx91x.c
Normal file
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@ -0,0 +1,429 @@
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/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/types.h>
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#include "rsi_rom_udma_wrapper.h"
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#include "rsi_udma.h"
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#include "sl_status.h"
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#define DT_DRV_COMPAT silabs_siwx91x_dma
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#define DMA_MAX_TRANSFER_COUNT 1024
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#define DMA_CH_PRIORITY_HIGH 1
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#define DMA_CH_PRIORITY_LOW 0
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#define VALID_BURST_LENGTH 0
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#define UDMA_ADDR_INC_NONE 0X03
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LOG_MODULE_REGISTER(si91x_dma, CONFIG_DMA_LOG_LEVEL);
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struct dma_siwx91x_config {
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UDMA0_Type *reg; /* UDMA register base address */
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uint8_t channels; /* UDMA channel count */
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uint8_t irq_number; /* IRQ number */
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RSI_UDMA_DESC_T *sram_desc_addr; /* SRAM Address for UDMA Descriptor Storage */
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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void (*irq_configure)(void); /* IRQ configure function */
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};
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struct dma_siwx91x_data {
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UDMA_Channel_Info *chan_info;
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dma_callback_t dma_callback; /* User callback */
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void *cb_data; /* User callback data */
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RSI_UDMA_DATACONTEXT_T dma_rom_buff; /* Buffer to store UDMA handle */
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/* related information */
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};
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static inline int siwx91x_dma_is_peripheral_request(uint32_t dir)
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{
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if (dir == MEMORY_TO_MEMORY) {
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return 0;
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}
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if (dir == MEMORY_TO_PERIPHERAL || dir == PERIPHERAL_TO_MEMORY) {
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return 1;
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}
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return -1;
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}
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static inline int siwx91x_dma_data_width(uint32_t data_width)
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{
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switch (data_width) {
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case 1:
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return SRC_SIZE_8;
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case 2:
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return SRC_SIZE_16;
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case 4:
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return SRC_SIZE_32;
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default:
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return -EINVAL;
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}
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}
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static inline int siwx91x_dma_burst_length(uint32_t blen)
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{
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switch (blen / 8) {
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case 1:
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return VALID_BURST_LENGTH; /* 8-bit burst */
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default:
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return -EINVAL;
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}
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}
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static inline int siwx91x_dma_addr_adjustment(uint32_t adjustment)
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{
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switch (adjustment) {
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case 0:
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return 0; /* Addr Increment */
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case 2:
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return UDMA_ADDR_INC_NONE; /* No Address increment */
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default:
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return -EINVAL;
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}
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}
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static int dma_channel_config(const struct device *dev, RSI_UDMA_HANDLE_T udma_handle,
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uint32_t channel, struct dma_config *config,
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UDMA_Channel_Info *channel_info)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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UDMA_RESOURCES udma_resources = {
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.reg = cfg->reg,
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.udma_irq_num = cfg->irq_number,
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/* SRAM address where UDMA descriptor is stored */
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.desc = cfg->sram_desc_addr,
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};
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RSI_UDMA_CHA_CONFIG_DATA_T channel_control = {
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.transferType = UDMA_MODE_BASIC,
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};
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RSI_UDMA_CHA_CFG_T channel_config = {};
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int status;
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channel_config.channelPrioHigh = config->channel_priority;
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if (siwx91x_dma_is_peripheral_request(config->channel_direction) < 0) {
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return -EINVAL;
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}
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channel_config.periphReq = siwx91x_dma_is_peripheral_request(config->channel_direction);
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channel_config.dmaCh = channel;
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if (channel_config.periphReq) {
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/* Arbitration power for peripheral<->memory transfers */
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channel_control.rPower = ARBSIZE_1;
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} else {
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/* Arbitration power for mem-mem transfers */
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channel_control.rPower = ARBSIZE_1024;
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}
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/* Obtain the number of transfers */
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config->head_block->block_size /= config->source_data_size;
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if (config->head_block->block_size >= DMA_MAX_TRANSFER_COUNT) {
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/* Maximum number of transfers is 1024 */
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channel_control.totalNumOfDMATrans = DMA_MAX_TRANSFER_COUNT - 1;
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} else {
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channel_control.totalNumOfDMATrans = config->head_block->block_size;
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}
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if (siwx91x_dma_data_width(config->source_data_size) < 0 ||
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siwx91x_dma_data_width(config->dest_data_size) < 0) {
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return -EINVAL;
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}
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if (siwx91x_dma_burst_length(config->source_burst_length) < 0 ||
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siwx91x_dma_burst_length(config->dest_burst_length) < 0) {
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return -EINVAL;
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}
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channel_control.srcSize = siwx91x_dma_data_width(config->source_data_size);
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channel_control.dstSize = siwx91x_dma_data_width(config->dest_data_size);
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if (siwx91x_dma_addr_adjustment(config->head_block->source_addr_adj) < 0 ||
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siwx91x_dma_addr_adjustment(config->head_block->dest_addr_adj) < 0) {
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return -EINVAL;
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}
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if (siwx91x_dma_addr_adjustment(config->head_block->source_addr_adj) == 0) {
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channel_control.srcInc = channel_control.srcSize;
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} else {
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channel_control.srcInc = UDMA_SRC_INC_NONE;
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}
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if (siwx91x_dma_addr_adjustment(config->head_block->dest_addr_adj) == 0) {
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channel_control.dstInc = channel_control.dstSize;
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} else {
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channel_control.dstInc = UDMA_DST_INC_NONE;
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}
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status = UDMAx_ChannelConfigure(&udma_resources, (uint8_t)channel,
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config->head_block->source_address,
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config->head_block->dest_address,
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config->head_block->block_size, channel_control,
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&channel_config, NULL, channel_info, udma_handle);
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if (status) {
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return -EIO;
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}
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return 0;
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}
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/* Function to configure UDMA channel for transfer */
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static int dma_siwx91x_configure(const struct device *dev, uint32_t channel,
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struct dma_config *config)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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struct dma_siwx91x_data *data = dev->data;
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void *udma_handle = &data->dma_rom_buff;
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int status;
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/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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/* Disable the channel before configuring */
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if (RSI_UDMA_ChannelDisable(udma_handle, channel) != 0) {
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return -EIO;
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}
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if (config->channel_priority != DMA_CH_PRIORITY_LOW &&
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config->channel_priority != DMA_CH_PRIORITY_HIGH) {
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return -EINVAL;
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}
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/* Configure dma channel for transfer */
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status = dma_channel_config(dev, udma_handle, channel, config, data->chan_info);
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if (status) {
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return status;
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}
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return 0;
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}
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/* Function to reload UDMA channel for new transfer */
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static int dma_siwx91x_reload(const struct device *dev, uint32_t channel, uint32_t src,
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uint32_t dst, size_t size)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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struct dma_siwx91x_data *data = dev->data;
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void *udma_handle = &data->dma_rom_buff;
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uint32_t desc_src_addr;
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uint32_t desc_dst_addr;
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uint32_t length;
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RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr;
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/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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/* Disable the channel before reloading transfer */
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if (RSI_UDMA_ChannelDisable(udma_handle, channel) != 0) {
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return -EIO;
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}
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/* Update new channel info to dev->data structure */
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data->chan_info[channel].SrcAddr = src;
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data->chan_info[channel].DestAddr = dst;
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data->chan_info[channel].Size = size;
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/* Update new transfer size to dev->data structure */
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if (size >= DMA_MAX_TRANSFER_COUNT) {
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data->chan_info[channel].Cnt = DMA_MAX_TRANSFER_COUNT - 1;
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} else {
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data->chan_info[channel].Cnt = size;
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}
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/* Program the DMA descriptors with new transfer data information. */
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if (udma_table[channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE) {
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length = data->chan_info[channel].Cnt
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<< udma_table[channel].vsUDMAChaConfigData1.srcInc;
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desc_src_addr = src + (length - 1);
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udma_table[channel].pSrcEndAddr = (void *)desc_src_addr;
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}
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if (udma_table[channel].vsUDMAChaConfigData1.dstInc != UDMA_SRC_INC_NONE) {
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length = data->chan_info[channel].Cnt
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<< udma_table[channel].vsUDMAChaConfigData1.dstInc;
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desc_dst_addr = dst + (length - 1);
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udma_table[channel].pDstEndAddr = (void *)desc_dst_addr;
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}
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udma_table[channel].vsUDMAChaConfigData1.totalNumOfDMATrans = data->chan_info[channel].Cnt;
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udma_table[channel].vsUDMAChaConfigData1.transferType = UDMA_MODE_BASIC;
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return 0;
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}
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/* Function to start a DMA transfer */
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static int dma_siwx91x_start(const struct device *dev, uint32_t channel)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr;
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struct dma_siwx91x_data *data = dev->data;
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void *udma_handle = &data->dma_rom_buff;
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/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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if (RSI_UDMA_ChannelEnable(udma_handle, channel) != 0) {
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return -EINVAL;
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}
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/* Check if the transfer type is memory-memory */
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if (udma_table[channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE &&
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udma_table[channel].vsUDMAChaConfigData1.dstInc != UDMA_DST_INC_NONE) {
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/* Apply software trigger to start transfer */
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cfg->reg->CHNL_SW_REQUEST |= BIT(channel);
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}
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return 0;
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}
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/* Function to stop a DMA transfer */
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static int dma_siwx91x_stop(const struct device *dev, uint32_t channel)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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struct dma_siwx91x_data *data = dev->data;
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void *udma_handle = &data->dma_rom_buff;
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/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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if (RSI_UDMA_ChannelDisable(udma_handle, channel) != 0) {
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return -EIO;
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}
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return 0;
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}
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/* Function to fetch DMA channel status */
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static int dma_siwx91x_get_status(const struct device *dev, uint32_t channel,
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struct dma_status *stat)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr;
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/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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/* Read the channel status register */
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if (cfg->reg->CHANNEL_STATUS_REG & BIT(channel)) {
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stat->busy = 1;
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} else {
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stat->busy = 0;
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}
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/* Obtain the transfer direction from channel descriptors */
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if (udma_table[channel].vsUDMAChaConfigData1.srcInc == UDMA_SRC_INC_NONE) {
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stat->dir = PERIPHERAL_TO_MEMORY;
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} else if (udma_table[channel].vsUDMAChaConfigData1.dstInc == UDMA_DST_INC_NONE) {
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stat->dir = MEMORY_TO_PERIPHERAL;
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} else {
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stat->dir = MEMORY_TO_MEMORY;
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}
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return 0;
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}
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/* Function to initialize DMA peripheral */
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static int dma_siwx91x_init(const struct device *dev)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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struct dma_siwx91x_data *data = dev->data;
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void *udma_handle = NULL;
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UDMA_RESOURCES udma_resources = {
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.reg = cfg->reg, /* UDMA register base address */
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.udma_irq_num = cfg->irq_number,
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.desc = cfg->sram_desc_addr,
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};
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int ret;
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ret = clock_control_on(cfg->clock_dev, cfg->clock_subsys);
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if (ret) {
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return ret;
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}
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udma_handle = UDMAx_Initialize(&udma_resources, udma_resources.desc, NULL,
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(uint32_t *)&data->dma_rom_buff);
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if (udma_handle != &data->dma_rom_buff) {
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return -EINVAL;
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}
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/* Connect the DMA interrupt */
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cfg->irq_configure();
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if (UDMAx_DMAEnable(&udma_resources, udma_handle) != 0) {
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return -EBUSY;
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}
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return 0;
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}
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static void dma_siwx91x_isr(const struct device *dev)
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{
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const struct dma_siwx91x_config *cfg = dev->config;
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struct dma_siwx91x_data *data = dev->data;
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UDMA_RESOURCES udma_resources = {
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.reg = cfg->reg,
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.udma_irq_num = cfg->irq_number,
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.desc = cfg->sram_desc_addr,
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};
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uint8_t channel;
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/* Disable the IRQ to prevent the ISR from being triggered by */
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/* interrupts from other DMA channels */
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irq_disable(cfg->irq_number);
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channel = find_lsb_set(cfg->reg->UDMA_DONE_STATUS_REG);
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/* Identify the interrupt channel */
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if (!channel || channel > cfg->channels) {
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goto out;
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}
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/* find_lsb_set() returns 1 indexed value */
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channel -= 1;
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if (data->chan_info[channel].Cnt == data->chan_info[channel].Size) {
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if (data->dma_callback) {
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/* Transfer complete, call user callback */
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data->dma_callback(dev, data->cb_data, channel, 0);
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}
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cfg->reg->UDMA_DONE_STATUS_REG = BIT(channel);
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} else {
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/* Call UDMA ROM IRQ handler. */
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ROMAPI_UDMA_WRAPPER_API->uDMAx_IRQHandler(&udma_resources, udma_resources.desc,
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data->chan_info);
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/* Is a Memory-to-memory Transfer */
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if (udma_resources.desc[channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE &&
|
||||
udma_resources.desc[channel].vsUDMAChaConfigData1.dstInc != UDMA_DST_INC_NONE) {
|
||||
/* Set the software trigger bit for starting next transfer */
|
||||
cfg->reg->CHNL_SW_REQUEST |= BIT(channel);
|
||||
}
|
||||
}
|
||||
out:
|
||||
/* Enable the IRQ to restore interrupt functionality for other DMA channels */
|
||||
irq_enable(cfg->irq_number);
|
||||
}
|
||||
|
||||
/* Store the Si91x DMA APIs */
|
||||
static DEVICE_API(dma, siwx91x_dma_api) = {
|
||||
.config = dma_siwx91x_configure,
|
||||
.reload = dma_siwx91x_reload,
|
||||
.start = dma_siwx91x_start,
|
||||
.stop = dma_siwx91x_stop,
|
||||
.get_status = dma_siwx91x_get_status,
|
||||
};
|
||||
|
||||
#define SIWX91X_DMA_INIT(inst) \
|
||||
static UDMA_Channel_Info dma##inst##_channel_info[DT_INST_PROP(inst, dma_channels)]; \
|
||||
static struct dma_siwx91x_data dma##inst##_data = { \
|
||||
.chan_info = dma##inst##_channel_info, \
|
||||
}; \
|
||||
static void siwx91x_dma##inst##_irq_configure(void) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_IRQ(inst, irq), DT_INST_IRQ(inst, priority), dma_siwx91x_isr, \
|
||||
DEVICE_DT_INST_GET(inst), 0); \
|
||||
irq_enable(DT_INST_IRQ(inst, irq)); \
|
||||
} \
|
||||
static const struct dma_siwx91x_config dma##inst##_cfg = { \
|
||||
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
|
||||
.clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \
|
||||
.reg = (UDMA0_Type *)DT_INST_REG_ADDR(inst), \
|
||||
.channels = DT_INST_PROP(inst, dma_channels), \
|
||||
.irq_number = DT_INST_PROP_BY_IDX(inst, interrupts, 0), \
|
||||
.sram_desc_addr = (RSI_UDMA_DESC_T *)DT_INST_PROP(inst, silabs_sram_desc_addr), \
|
||||
.irq_configure = siwx91x_dma##inst##_irq_configure, \
|
||||
}; \
|
||||
DEVICE_DT_INST_DEFINE(inst, &dma_siwx91x_init, NULL, &dma##inst##_data, &dma##inst##_cfg, \
|
||||
PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &siwx91x_dma_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(SIWX91X_DMA_INIT)
|
||||
26
dts/bindings/dma/silabs,siwx91x-dma.yaml
Normal file
26
dts/bindings/dma/silabs,siwx91x-dma.yaml
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
description: Silabs SiWx91x DMA node
|
||||
|
||||
compatible: "silabs,siwx91x-dma"
|
||||
|
||||
include: dma-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
silabs,sram-desc-addr:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
SRAM Address for UDMA Descriptor Storage. This address must correspond to the location
|
||||
of the udma_addr0 section in the linker script for the dma0 node, and the udma_addr1
|
||||
section for the ulpdma node. Ensure that the value specified for the SRAM address matches
|
||||
the respective section defined in the linker file for each UDMA node, as this alignment
|
||||
is critical for proper descriptor management and data transfer.
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
|
||||
# Parameter syntax
|
||||
dma-cells:
|
||||
- channel
|
||||
|
|
@ -54,5 +54,13 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_SILABS_SIWX91X
|
|||
${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_rng.c
|
||||
)
|
||||
|
||||
zephyr_compile_definitions_ifdef(CONFIG_DMA_SILABS_SIWX91X
|
||||
UDMA_ROMDRIVER_PRESENT
|
||||
)
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_DMA_SILABS_SIWX91X
|
||||
${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/rom_driver/src/rsi_rom_table_si91x.c
|
||||
)
|
||||
|
||||
zephyr_linker_sources(ROM_SECTIONS linker/code_classification_text.ld)
|
||||
zephyr_linker_sources(RAMFUNC_SECTION linker/code_classification_ramfunc.ld)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue