michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: stm32: Remove useless CONFIG_BOARD_FOO from _defconfig files

Browse source 
CONFIG_BOARD_FOO is enabled in a number of board *_defconfig files
although it is useless as it is set by default (as defined as a
one option choice, symbol defaults to 'y').
CONFIG_BOARD_FOO should remain only in target that are defined
in boards providing multiple choices (dual cores, board with multiple
revisions).

Clean it from STM32 impacted boards.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-01-29 15:23:33 +01:00 • committed by Kumar Gala
commit 124004c29a
51 changed files with 6 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

1
boards/arm/96b_avenger96/96b_avenger96_defconfig
View file

@ -1,5 +1,4 @@
CONFIG_ARM=y
CONFIG_BOARD_96B_AVENGER96=y
CONFIG_SOC_SERIES_STM32MP1X=y
CONFIG_SOC_STM32MP15_M4=y
# 209 MHz system clock (mlhclk_ck)

1
boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_96B_STM32_SENSOR_MEZ=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F446XX=y

1
boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
# Platform Configuration
CONFIG_SOC_STM32F030X8=y
CONFIG_BOARD_NUCLEO_F030R8=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

1
boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
# Platform Configuration
CONFIG_SOC_STM32F070XB=y
CONFIG_BOARD_NUCLEO_F070RB=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

1
boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
# Platform Configuration
CONFIG_SOC_STM32F091XC=y
CONFIG_BOARD_NUCLEO_F091RC=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

1
boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F103RB=y
CONFIG_SOC_SERIES_STM32F1X=y
CONFIG_SOC_STM32F103XB=y
# 72MHz system clock

1
boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F207ZG=y
CONFIG_SOC_SERIES_STM32F2X=y
CONFIG_SOC_STM32F207XX=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000

1
boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F3X=y
# Platform Configuration
CONFIG_SOC_STM32F334X8=y
CONFIG_BOARD_NUCLEO_F334R8=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000

1
boards/arm/nucleo_f401re/nucleo_f401re_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F401RE=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F401XE=y
# 84MHz system clock

1
boards/arm/nucleo_f411re/nucleo_f411re_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F411RE=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F411XE=y
# 96MHz system clock (highest value to get a precise USB clock)

1
boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F412ZG=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F412ZG=y
# 96MHz system clock (highest value to get a precise USB clock)

1
boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F413ZH=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F413XX=y
# 96MHz system clock (highest value to get a precise USB clock)

1
boards/arm/nucleo_f446re/nucleo_f446re_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F446RE=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F446XX=y
# 96MHz system clock (highest value to get a precise USB clock)

1
boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F746ZG=y
CONFIG_SOC_SERIES_STM32F7X=y
CONFIG_SOC_STM32F746XX=y
# 72MHz system clock (CubeMX Defaults)

1
boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F756ZG=y
CONFIG_SOC_SERIES_STM32F7X=y
CONFIG_SOC_STM32F756XX=y
# 72MHz system clock (CubeMX Defaults)

1
boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_NUCLEO_F767ZI=y
CONFIG_SOC_SERIES_STM32F7X=y
CONFIG_SOC_STM32F767XX=y
# 72MHz system clock (CubeMX Defaults)

1
boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig
View file

@ -2,7 +2,6 @@
CONFIG_ARM=y
CONFIG_SOC_SERIES_STM32G0X=y
CONFIG_SOC_STM32G071XX=y
CONFIG_BOARD_NUCLEO_G071RB=y
# Enable MPU
CONFIG_ARM_MPU=y

1
boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32L0X=y
# Platform Configuration
CONFIG_SOC_STM32L053XX=y
CONFIG_BOARD_NUCLEO_L053R8=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000

1
boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32L0X=y
# Platform Configuration
CONFIG_SOC_STM32L073XX=y
CONFIG_BOARD_NUCLEO_L073RZ=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000

1
boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig
View file

@ -3,7 +3,6 @@
CONFIG_ARM=y
CONFIG_SOC_SERIES_STM32L4X=y
CONFIG_SOC_STM32L4R5XX=y
CONFIG_BOARD_NUCLEO_L4R5ZI=y
# 120MHz system clock only in 'boost power' mode. DM00310109, section
# 5.1.7 states that the R1MODE bit must be cleared before system can

1
boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_OLIMEX_STM32_E407=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F407XG=y
# 168MHz system clock

1
boards/arm/olimex_stm32_h407/olimex_stm32_h407_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_OLIMEX_STM32_H407=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F407XG=y
# 168MHz system clock

1
boards/arm/olimex_stm32_p405/olimex_stm32_p405_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_OLIMEX_STM32_P405=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F405XG=y
# 168MHz system clock

1
boards/arm/olimexino_stm32/olimexino_stm32_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_OLIMEXINO_STM32=y
CONFIG_SOC_SERIES_STM32F1X=y
CONFIG_SOC_STM32F103XB=y
# 72MHz system clock

1
boards/arm/sensortile_box/sensortile_box_defconfig
View file

@ -3,7 +3,6 @@
CONFIG_ARM=y
CONFIG_SOC_SERIES_STM32L4X=y
CONFIG_SOC_STM32L4R9XX=y
CONFIG_BOARD_SENSORTILE_BOX=y
# 120MHz system clock only in 'boost power' mode. DM00310109, section
# 5.1.7 states that the R1MODE bit must be cleared before system can

1
boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STEVAL_FCU001V1=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F401XC=y

1
boards/arm/stm3210c_eval/stm3210c_eval_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F1X=y
# Platform Configuration
CONFIG_SOC_STM32F107XC=y
CONFIG_BOARD_STM3210C_EVAL=y
# General Kernel Options
# 72MHz system clock

1
boards/arm/stm32373c_eval/stm32373c_eval_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F3X=y
# Platform Configuration
CONFIG_SOC_STM32F373XC=y
CONFIG_BOARD_STM32373C_EVAL=y
# Floating Point Options
CONFIG_FLOAT=y

1
boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig
View file

@ -6,7 +6,6 @@
#
CONFIG_ARM=y
CONFIG_BOARD_STM32_MIN_DEV_BLACK=y
CONFIG_SOC_SERIES_STM32F1X=y
CONFIG_SOC_STM32F103X8=y

1
boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32_MIN_DEV_BLUE=y
CONFIG_SOC_SERIES_STM32F1X=y
CONFIG_SOC_STM32F103X8=y

1
boards/arm/stm32f030_demo/stm32f030_demo_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
# Platform Configuration
CONFIG_SOC_STM32F030X4=y
CONFIG_BOARD_STM32F030_DEMO=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

1
boards/arm/stm32f072_eval/stm32f072_eval_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
# Platform Configuration
CONFIG_SOC_STM32F072XB=y
CONFIG_BOARD_STM32F072_EVAL=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

1
boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
# Platform Configuration
CONFIG_SOC_STM32F072XB=y
CONFIG_BOARD_STM32F072B_DISCO=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

1
boards/arm/stm32f0_disco/stm32f0_disco_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_SOC_SERIES_STM32F0X=y
# Platform Configuration
CONFIG_SOC_STM32F051X8=y
CONFIG_BOARD_STM32F0_DISCO=y
# General Kernel Options
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

1
boards/arm/stm32f3_disco/stm32f3_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F3_DISCO=y
CONFIG_SOC_SERIES_STM32F3X=y
CONFIG_SOC_STM32F303XC=y
# 72MHz system clock

1
boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F411E_DISCO=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F411XE=y
# 100MHz system clock (highest value to get a precise USB clock should be 96MHz)

1
boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F412G_DISCO=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F412ZG=y
# 100MHz system clock (highest value to get a precise USB clock should be 96MHz)

1
boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F429I_DISC1=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F429XX=y
# 168MHz system clock

1
boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F469I_DISCO=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F469XX=y
# 180MHz system clock

1
boards/arm/stm32f4_disco/stm32f4_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F4_DISCO=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F407XG=y
# 168MHz system clock

1
boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F723E_DISCO=y
CONFIG_SOC_SERIES_STM32F7X=y
CONFIG_SOC_STM32F723XX=y
# 216MHz system clock

1
boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F746G_DISCO=y
CONFIG_SOC_SERIES_STM32F7X=y
CONFIG_SOC_STM32F746XX=y
# 216MHz system clock

1
boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32F769I_DISCO=y
CONFIG_SOC_SERIES_STM32F7X=y
CONFIG_SOC_STM32F769XX=y
# 216MHz system clock

1
boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig
View file

@ -3,7 +3,6 @@ CONFIG_ARM=y
CONFIG_SOC_SERIES_STM32G0X=y
CONFIG_SOC_STM32G031XX=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_BOARD_STM32G0316_DISCO=y
# 64MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=64000000

4
boards/arm/stm32h747i_disco/stm32h747i_disco_m4_defconfig
View file

@ -1,10 +1,12 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32H747I_DISCO_M4=y
CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H747XX=y
# Board config should be specified since there are 2 possible targets
CONFIG_BOARD_STM32H747I_DISCO_M4=y
# enable pinmux
CONFIG_PINMUX=y

4
boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig
View file

@ -1,10 +1,12 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32H747I_DISCO_M7=y
CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H747XX=y
# Board config should be specified since there are 2 possible targets
CONFIG_BOARD_STM32H747I_DISCO_M7=y
# enable pinmux
CONFIG_PINMUX=y

1
boards/arm/stm32l1_disco/stm32l1_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32L1_DISCO=y
CONFIG_SOC_SERIES_STM32L1X=y
CONFIG_SOC_STM32L151XB=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000

1
boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32L476G_DISCO=y
CONFIG_SOC_SERIES_STM32L4X=y
CONFIG_SOC_STM32L476XX=y
# 80MHz system clock

1
boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM=y
CONFIG_BOARD_STM32L496G_DISCO=y
CONFIG_SOC_SERIES_STM32L4X=y
CONFIG_SOC_STM32L496XX=y
# 80MHz system clock

1
boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig
View file

@ -1,5 +1,4 @@
CONFIG_ARM=y
CONFIG_BOARD_STM32MP157C_DK2=y
CONFIG_SOC_SERIES_STM32MP1X=y
CONFIG_SOC_STM32MP15_M4=y
# 209 MHz system clock (mlhclk_ck)

1
boards/arm/stm32vl_disco/stm32vl_disco_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_ARM=y
# Platform Configuration
CONFIG_SOC_SERIES_STM32F1X=y
CONFIG_SOC_STM32F100XB=y
CONFIG_BOARD_STM32VL_DISCO=y
# 24MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000