dts: mcxn547: add dts for MCXN547

Add SOC DTS for MCXN547.
Reorganizes DTS with a common file for MXNx4x SoCs.

Signed-off-by: Alexandre Rey <alexandre.rey@swisstiming.com>

dts/arm/nxp/nxp_mcxn54x.dtsi

@@ -0,0 +1,38 @@
+/*
+ * Copyright 2025 Swiss Timing Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+
+/ {
+	soc {
+		sram: sram@14000000 {
+			ranges = <0x4000000 0x14000000 0x20000000>;
+		};
+
+		peripheral: peripheral@50000000 {
+			ranges = <0x0 0x50000000 0x10000000>;
+
+			ftfe: flash-controller@43000 {
+				ranges = <0x0 0x10000000 0x4000000>;
+			};
+		};
+
+		flexspi: spi@500c8000 {
+			reg = <0x500c8000 0x1000>, <0x90000000 DT_SIZE_M(8)>;
+		};
+	};
+};
+
+#include "nxp_mcxnx4x_common.dtsi"
+
+/*
+ * Explicitly enable FMU after we include the common dtsi file,
+ * which will set it to disabled.
+ */
+&fmu {
+	status = "okay";
+};

dts/arm/nxp/nxp_mcxn54x_ns.dtsi

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2025 Swiss Timing Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+
+/ {
+	soc {
+		sram: sram@4000000 {
+			ranges = <0x4000000 0x4000000 0x20000000>;
+		};
+
+		peripheral: peripheral@40000000 {
+			ranges = <0x0 0x40000000 0x10000000>;
+		};
+
+		flexspi: spi@400c8000 {
+			reg = <0x400c8000 0x1000>, <0x80000000 DT_SIZE_M(8)>;
+		};
+	};
+};
+
+#include "nxp_mcxnx4x_common.dtsi"