drivers: adc: Add ADC driver for MAX32xxx MCUs
Added ADC driver for MAX32xxx MCUs Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com> Co-authored-by: Okan Sahin <okan.sahin@analog.com> Co-authored-by: Sadik Ozer <sadik.ozer@analog.com>
This commit is contained in:
Furkan Akkiz
Carles Cufí
parent
ac3f4c8dce
commit
11a172a610
4 changed files with 355 additions and 0 deletions
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@ -53,3 +53,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB1200 adc_ene_kb1200.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_GAU adc_mcux_gau_adc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AMBIQ adc_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RA adc_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MAX32 adc_max32.c)
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@ -132,4 +132,6 @@ source "drivers/adc/Kconfig.ambiq"
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source "drivers/adc/Kconfig.renesas_ra"
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source "drivers/adc/Kconfig.max32"
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endif # ADC
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12
drivers/adc/Kconfig.max32
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12
drivers/adc/Kconfig.max32
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@ -0,0 +1,12 @@
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# ADI SoC ADC configuration options
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# Copyright (c) 2023-2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config ADC_MAX32
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bool "MAX32 ADC driver"
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default y
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depends on DT_HAS_ADI_MAX32_ADC_ENABLED
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select PINCTRL
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help
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Enable ADC driver for ADI MAX32xxx MCUs.
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340
drivers/adc/adc_max32.c
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340
drivers/adc/adc_max32.c
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@ -0,0 +1,340 @@
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/*
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* Copyright (c) 2023-2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT adi_max32_adc
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(adc_max32, CONFIG_ADC_LOG_LEVEL);
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#include <wrap_max32_adc.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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/* reference voltage for the ADC */
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#define MAX32_ADC_VREF_MV DT_INST_PROP(0, vref_mv)
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struct max32_adc_config {
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uint8_t channel_count;
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mxc_adc_regs_t *regs;
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int clock_divider;
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int track_count;
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int idle_count;
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const struct pinctrl_dev_config *pctrl;
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const struct device *clock;
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struct max32_perclk perclk;
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void (*irq_func)(void);
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};
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struct max32_adc_data {
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const struct device *dev;
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struct adc_context ctx;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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uint32_t channels;
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uint32_t sample_channels;
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const uint8_t resolution;
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};
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#ifdef CONFIG_ADC_ASYNC
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static void adc_complete_cb(void *req, int error)
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{
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ARG_UNUSED(req);
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ARG_UNUSED(error);
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}
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#endif /* CONFIG_ADC_ASYNC */
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static void adc_max32_start_channel(const struct device *dev)
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{
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struct max32_adc_data *data = dev->data;
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int ret = 0;
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#if defined(CONFIG_ADC_ASYNC)
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if (data->ctx.asynchronous) {
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ret = Wrap_MXC_ADC_StartConversionAsync(&data->sample_channels, adc_complete_cb);
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if (ret < 0) {
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LOG_ERR("Error starting conversion (%d)", ret);
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}
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} else {
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#endif /* CONFIG_ADC_ASYNC */
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while (data->sample_channels) {
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ret = Wrap_MXC_ADC_StartConversion(&data->sample_channels);
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if (ret < 0) {
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LOG_ERR("Error starting conversion (%d)", ret);
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return;
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}
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Wrap_MXC_ADC_GetData(&data->buffer);
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}
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Wrap_MXC_ADC_DisableConversion();
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adc_context_on_sampling_done(&data->ctx, dev);
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#if defined(CONFIG_ADC_ASYNC)
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}
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#endif /* CONFIG_ADC_ASYNC */
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct max32_adc_data *data = CONTAINER_OF(ctx, struct max32_adc_data, ctx);
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data->sample_channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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adc_max32_start_channel(data->dev);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct max32_adc_data *data = CONTAINER_OF(ctx, struct max32_adc_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static int start_read(const struct device *dev, const struct adc_sequence *seq)
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{
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struct max32_adc_data *data = dev->data;
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uint32_t num_of_sample_channels = POPCOUNT(seq->channels);
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uint32_t num_of_sample = 1;
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int ret = 0;
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if (seq->resolution != data->resolution) {
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LOG_ERR("Unsupported resolution (%d)", seq->resolution);
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return -ENOTSUP;
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}
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if (seq->channels == 0) {
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return -EINVAL;
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}
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if ((data->channels & seq->channels) != seq->channels) {
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return -EINVAL;
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}
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ret = Wrap_MXC_ADC_AverageConfig(seq->oversampling);
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if (ret != 0) {
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return -EINVAL;
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}
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if (seq->options) {
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num_of_sample += seq->options->extra_samplings;
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}
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if (seq->buffer_size < (num_of_sample * num_of_sample_channels)) { /* Buffer size control */
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return -ENOMEM;
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}
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data->buffer = seq->buffer;
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adc_context_start_read(&data->ctx, seq);
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return adc_context_wait_for_completion(&data->ctx);
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}
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static int adc_max32_read(const struct device *dev, const struct adc_sequence *seq)
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{
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struct max32_adc_data *data = dev->data;
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int ret;
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adc_context_lock(&data->ctx, false, NULL);
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ret = start_read(dev, seq);
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adc_context_release(&data->ctx, ret);
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return ret;
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}
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#ifdef CONFIG_ADC_ASYNC
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static int adc_max32_read_async(const struct device *dev, const struct adc_sequence *seq,
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struct k_poll_signal *async)
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{
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struct max32_adc_data *data = dev->data;
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int ret;
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adc_context_lock(&data->ctx, true, async);
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ret = start_read(dev, seq);
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adc_context_release(&data->ctx, ret);
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return ret;
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}
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#endif /* CONFIG_ADC_ASYNC */
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static int adc_max32_channel_setup(const struct device *dev, const struct adc_channel_cfg *cfg)
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{
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const struct max32_adc_config *conf = dev->config;
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struct max32_adc_data *data = dev->data;
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wrap_mxc_adc_scale_t wrap_mxc_scale;
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uint8_t adc_reference;
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int ret = 0;
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if (cfg->channel_id >= conf->channel_count) {
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LOG_ERR("Invalid channel (%u)", cfg->channel_id);
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return -EINVAL;
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}
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if (cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Invalid channel acquisition time");
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return -EINVAL;
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}
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if (cfg->differential) {
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LOG_ERR("Differential sampling not supported");
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return -ENOTSUP;
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}
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switch (cfg->reference) {
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case ADC_REF_INTERNAL:
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adc_reference = ADI_MAX32_ADC_REF_INTERNAL;
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break;
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case ADC_REF_VDD_1_2:
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adc_reference = ADI_MAX32_ADC_REF_VDD_1_2;
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break;
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case ADC_REF_EXTERNAL0:
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adc_reference = ADI_MAX32_ADC_REF_EXT0;
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break;
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default:
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return -ENOTSUP;
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}
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ret = Wrap_MXC_ADC_ReferenceSelect(adc_reference);
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if (ret != 0) {
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LOG_ERR("Reference is not supported.");
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return -ENOTSUP;
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}
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switch (cfg->gain) {
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case ADC_GAIN_1_6:
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wrap_mxc_scale = WRAP_MXC_ADC_SCALE_6;
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break;
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case ADC_GAIN_1_4:
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wrap_mxc_scale = WRAP_MXC_ADC_SCALE_4;
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break;
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case ADC_GAIN_1_3:
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wrap_mxc_scale = WRAP_MXC_ADC_SCALE_3;
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break;
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case ADC_GAIN_1_2:
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wrap_mxc_scale = WRAP_MXC_ADC_SCALE_2;
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break;
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case ADC_GAIN_1:
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wrap_mxc_scale = WRAP_MXC_ADC_SCALE_1;
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break;
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case ADC_GAIN_2:
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wrap_mxc_scale = WRAP_MXC_ADC_SCALE_2X;
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break;
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default:
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return -ENOTSUP;
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}
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ret = Wrap_MXC_ADC_SetExtScale(wrap_mxc_scale);
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if (ret != 0) {
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LOG_ERR("Gain value is not supported.");
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return -ENOTSUP;
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}
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data->channels |= BIT(cfg->channel_id);
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return 0;
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}
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static int adc_max32_init(const struct device *dev)
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{
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const struct max32_adc_config *config = dev->config;
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struct max32_adc_data *data = dev->data;
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uint32_t ret;
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wrap_mxc_adc_req_t req = {
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.clock = config->perclk.clk_src,
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.clkdiv = config->clock_divider,
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.cal = 1, /* Initial calibration enabled. */
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.ref = 1, /* Reference set to internal reference until user define it. */
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.trackCount = config->track_count,
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.idleCount = config->idle_count};
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/* Enable clock */
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ret = clock_control_on(config->clock, (clock_control_subsys_t)&config->perclk);
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if (ret) {
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return ret;
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}
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ret = Wrap_MXC_ADC_Init(&req);
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if (ret) {
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return -EINVAL;
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}
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ret = pinctrl_apply_state(config->pctrl, PINCTRL_STATE_DEFAULT);
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if (ret) {
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return ret;
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}
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config->irq_func();
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data->dev = dev;
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static void adc_max32_isr(const struct device *dev)
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{
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struct max32_adc_data *const data = dev->data;
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uint32_t flags = MXC_ADC_GetFlags();
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MXC_ADC_Handler();
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MXC_ADC_ClearFlags(flags);
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if (flags & WRAP_MXC_F_ADC_CONV_DONE_IF) {
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Wrap_MXC_ADC_GetData(&data->buffer);
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if (data->sample_channels != 0) {
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adc_max32_start_channel(dev);
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} else {
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Wrap_MXC_ADC_DisableConversion();
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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}
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static const struct adc_driver_api adc_max32_driver_api = {
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.channel_setup = adc_max32_channel_setup,
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.read = adc_max32_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = adc_max32_read_async,
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#endif /* CONFIG_ADC_ASYNC */
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.ref_internal = MAX32_ADC_VREF_MV,
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};
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#define MAX32_ADC_INIT(_num) \
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PINCTRL_DT_INST_DEFINE(_num); \
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static void max32_adc_irq_init_##_num(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority), adc_max32_isr, \
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DEVICE_DT_INST_GET(_num), 0); \
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irq_enable(DT_INST_IRQN(_num)); \
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}; \
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static const struct max32_adc_config max32_adc_config_##_num = { \
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.channel_count = DT_INST_PROP(_num, channel_count), \
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.regs = (mxc_adc_regs_t *)DT_INST_REG_ADDR(_num), \
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.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
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.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
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.clock_divider = DT_INST_PROP_OR(_num, clock_divider, 1), \
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.track_count = DT_INST_PROP_OR(_num, track_count, 0), \
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.idle_count = DT_INST_PROP_OR(_num, idle_count, 0), \
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.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
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.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
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.perclk.clk_src = \
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DT_INST_PROP_OR(_num, clock_source, ADI_MAX32_PRPH_CLK_SRC_PCLK), \
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.irq_func = max32_adc_irq_init_##_num, \
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}; \
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static struct max32_adc_data max32_adc_data_##_num = { \
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ADC_CONTEXT_INIT_TIMER(max32_adc_data_##_num, ctx), \
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ADC_CONTEXT_INIT_LOCK(max32_adc_data_##_num, ctx), \
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ADC_CONTEXT_INIT_SYNC(max32_adc_data_##_num, ctx), \
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.resolution = DT_INST_PROP(_num, resolution), \
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}; \
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DEVICE_DT_INST_DEFINE(_num, &adc_max32_init, NULL, &max32_adc_data_##_num, \
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&max32_adc_config_##_num, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
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&adc_max32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(MAX32_ADC_INIT)
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