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Microchip: XEC GPIO driver interrupt enable fix part 2

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Fixes issue 34879
This PR updates previous PR's 37138 and 37139.
Refer to issue 34879 for information from MCHP HW
designers. A delay after enabling interrupts is a
more appropriate work-around than depending upon
behavior of ARM DMB instruction.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley 2021-08-05 14:32:48 -04:00 • committed by Christopher Friedt
commit 114b84a58b
2 changed files with 13 additions and 9 deletions
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12
drivers/gpio/gpio_mchp_xec_v2.c
View file

@ -14,7 +14,7 @@
#include "gpio_utils.h"
#define XEC_ECIA_REGS ((struct ecia_regs *)(DT_REG_ADDR(DT_NODELABEL(ecia))))
#define XEC_GPIO_EDGE_DLY_COUNT 4
static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
(MCHP_GPIO_PORT_A_BITMAP),
@ -268,7 +268,6 @@ static int gpio_xec_pin_interrupt_configure(const struct device *dev,
} else {
pcr1 |= MCHP_GPIO_CTRL_IDET_LVL_LO;
}
sys_write32(pcr1, pcr1_addr);
} else if (mode == GPIO_INT_MODE_EDGE) {
if (trig == GPIO_INT_TRIG_LOW) {
pcr1 |= MCHP_GPIO_CTRL_IDET_FEDGE;
@ -277,11 +276,14 @@ static int gpio_xec_pin_interrupt_configure(const struct device *dev,
} else if (trig == GPIO_INT_TRIG_BOTH) {
pcr1 |= MCHP_GPIO_CTRL_IDET_BEDGE;
}
sys_write32(pcr1, pcr1_addr);
__DMB(); /* insure write completes */
} else {
pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
sys_write32(pcr1, pcr1_addr);
}
sys_write32(pcr1, pcr1_addr);
/* delay for HW to synchronize after it ungates its clock */
for (int i = 0; i < XEC_GPIO_EDGE_DLY_COUNT; i++) {
sys_read32(pcr1_addr);
}
mchp_soc_ecia_girq_src_clr(config->girq_id, pin);