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soc/arm/renesas_rzt2m: set default System Clock Control register values

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Introduced changes to set the default values
for clock control registers

Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
This commit is contained in:
Jan Bylicki 2023-12-13 13:53:17 +01:00 • committed by Henrik Brix Andersen
commit 112bcb229c
3 changed files with 88 additions and 0 deletions
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45
soc/renesas/rzt2m/soc.c
View file

@ -12,6 +12,8 @@
static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn));
static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs));
static const struct device *const sckcr_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr));
static const struct device *const sckcr2_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr2));
void rzt2m_unlock_prcrn(uint32_t mask)
{
@ -55,6 +57,32 @@ void rzt2m_lock_prcrs(uint32_t mask)
syscon_write_reg(prcrs_dev, 0, prcrs);
}
void rzt2m_set_sckcr2(uint32_t mask)
{
syscon_write_reg(sckcr2_dev, 0, mask);
}
uint32_t rzt2m_get_sckcr2(void)
{
uint32_t reg;
syscon_read_reg(sckcr2_dev, 0, &reg);
return reg;
}
void rzt2m_set_sckcr(uint32_t mask)
{
syscon_write_reg(sckcr_dev, 0, mask);
}
uint32_t rzt2m_get_sckcr(void)
{
uint32_t reg;
syscon_read_reg(sckcr_dev, 0, &reg);
return reg;
}
void rzt2m_enable_counters(void)
{
const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(gsc));
@ -68,6 +96,23 @@ static int rzt2m_init(void)
* so that device drivers can access configuration registers of peripherals.
*/
/* After the device drivers are done, lock the Protect Registers. */
rzt2m_unlock_prcrs(PRCRS_GPIO | PRCRS_CLK);
rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
/* Reset the System Clock Control Registers to default values */
rzt2m_set_sckcr(
CLMASEL |
PHYSEL |
FSELCANFD |
FSELXSPI0_DEFAULT |
FSELXSPI1_DEFAULT |
CKIO_DEFAULT
);
rzt2m_set_sckcr2(FSELCPU0_DEFAULT | FSELCPU1_DEFAULT);
rzt2m_lock_prcrs(PRCRS_GPIO | PRCRS_CLK);
rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
rzt2m_enable_counters();
return 0;

29
soc/renesas/rzt2m/soc.h
View file

@ -27,6 +27,30 @@
#define PRCRN_PRC1 BIT(1)
#define PRCRN_PRC2 BIT(2)
#define SCI4ASYNCSEL BIT(31)
#define SCI3ASYNCSEL BIT(30)
#define SCI2ASYNCSEL BIT(29)
#define SCI1ASYNCSEL BIT(28)
#define SCI0ASYNCSEL BIT(27)
#define SPI2ASYNCSEL BIT(26)
#define SPI1ASYNCSEL BIT(25)
#define SPI0ASYNCSEL BIT(24)
#define CLMASEL BIT(22)
#define PHYSEL BIT(21)
#define FSELCANFD BIT(20)
#define DIVSELXSPI1 BIT(14)
#define DIVSELXSPI0 BIT(6)
#define CKIO_DEFAULT BIT(17)
#define FSELXSPI1_DEFAULT GENMASK(10, 9)
#define FSELXSPI0_DEFAULT GENMASK(2, 1)
#define SCI5ASYNCSEL BIT(25)
#define SPI3ASYNCSEL BIT(24)
#define DIVSELSUB BIT(5)
#define FSELCPU1_DEFAULT 0b10 << 2
#define FSELCPU0_DEFAULT 0b10 << 0
/* PRC Key Code - this value is required to allow any write operation
* to the PRCRS / PRCRN registers.
* See section 10.2 of the RZ/T2M User's Manual: Hardware.
@ -38,4 +62,9 @@ void rzt2m_lock_prcrn(uint32_t mask);
void rzt2m_unlock_prcrs(uint32_t mask);
void rzt2m_lock_prcrs(uint32_t mask);
void rzt2m_set_sckcr2(uint32_t mask);
uint32_t rzt2m_get_sckcr2(void);
void rzt2m_set_sckcr(uint32_t mask);
uint32_t rzt2m_get_sckcr(void);
#endif /* _SOC__H_ */