diff --git a/tests/drivers/pinctrl/gd32/CMakeLists.txt b/tests/drivers/pinctrl/gd32/CMakeLists.txt
index 898ed03c804..0595ab19801 100644
--- a/tests/drivers/pinctrl/gd32/CMakeLists.txt
+++ b/tests/drivers/pinctrl/gd32/CMakeLists.txt
@@ -9,4 +9,6 @@ project(pinctrl_gd32)
 target_sources(app PRIVATE ../common/test_device.c)
 if(CONFIG_PINCTRL_GD32_AF)
   target_sources(app PRIVATE src/main_af.c)
+elseif(CONFIG_PINCTRL_GD32_AFIO)
+  target_sources(app PRIVATE src/main_afio.c)
 endif()
diff --git a/tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay b/tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay
new file mode 100644
index 00000000000..08255bf6517
--- /dev/null
+++ b/tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define GD32_TEST_DEVICE_RMP GD32_REMAP(0, 0, 0x1U, 1)
+
+/ {
+	test_device: test_device {
+		compatible = "vnd,pinctrl-device";
+		pinctrl-0 = <&test_device_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&pinctrl {
+	test_device_default: test_device_default {
+		/* Note: the groups are just meant for testing if properties and
+		   pins are parsed correctly, but do not necessarily represent a
+		   feasible combination */
+		pins1 {
+			pinmux = <GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)>,
+				 <GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP)>,
+				 <GD32_PINMUX_AFIO('C', 2, GPIO_IN, NORMP)>;
+		};
+		pins2 {
+			pinmux = <GD32_PINMUX_AFIO('A', 3, GPIO_IN, TEST_DEVICE_RMP)>,
+				 <GD32_PINMUX_AFIO('B', 4, ALTERNATE, TEST_DEVICE_RMP)>;
+		};
+		pins3 {
+			pinmux = <GD32_PINMUX_AFIO('C', 5, GPIO_IN, NORMP)>;
+			drive-push-pull;
+		};
+		pins4 {
+			pinmux = <GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP)>;
+			drive-open-drain;
+		};
+		pins5 {
+			pinmux = <GD32_PINMUX_AFIO('B', 7, GPIO_IN, NORMP)>;
+			bias-disable;
+		};
+		pins6 {
+			pinmux = <GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP)>;
+			bias-pull-up;
+		};
+		pins7 {
+			pinmux = <GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)>;
+			bias-pull-down;
+		};
+		pins8 {
+			pinmux = <GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP)>;
+			slew-rate = "max-speed-2mhz";
+		};
+		pins9 {
+			pinmux = <GD32_PINMUX_AFIO('C', 11, ALTERNATE, NORMP)>;
+			slew-rate = "max-speed-10mhz";
+		};
+		pins10 {
+			pinmux = <GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)>;
+			slew-rate = "max-speed-50mhz";
+		};
+		pins11 {
+			pinmux = <GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)>;
+			slew-rate = "max-speed-highest";
+		};
+	};
+};
diff --git a/tests/drivers/pinctrl/gd32/src/main_afio.c b/tests/drivers/pinctrl/gd32/src/main_afio.c
new file mode 100644
index 00000000000..97ad8550eec
--- /dev/null
+++ b/tests/drivers/pinctrl/gd32/src/main_afio.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <drivers/pinctrl.h>
+#include <ztest.h>
+
+/* pin configuration for test device */
+#define TEST_DEVICE DT_NODELABEL(test_device)
+PINCTRL_DT_DEV_CONFIG_DECLARE(TEST_DEVICE);
+static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(TEST_DEVICE);
+
+static void test_dt_extract(void)
+{
+	const struct pinctrl_state *scfg;
+	pinctrl_soc_pin_t pin;
+
+	zassert_equal(pcfg->state_cnt, 1U, NULL);
+
+	scfg = &pcfg->states[0];
+
+	zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT, NULL);
+	zassert_equal(scfg->pin_cnt, 14U, NULL);
+
+	pin = scfg->pins[0];
+	zassert_equal(GD32_PORT_GET(pin), 0, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 0, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ANALOG, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+
+	pin = scfg->pins[1];
+	zassert_equal(GD32_PORT_GET(pin), 1, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 1, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
+
+	pin = scfg->pins[2];
+	zassert_equal(GD32_PORT_GET(pin), 2, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 2, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
+	zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
+
+	pin = scfg->pins[3];
+	zassert_equal(GD32_PORT_GET(pin), 0, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 3, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
+	zassert_equal(GD32_REMAP_REG_GET(GD32_REMAP_GET(pin)), 0, NULL);
+	zassert_equal(GD32_REMAP_POS_GET(GD32_REMAP_GET(pin)), 0, NULL);
+	zassert_equal(GD32_REMAP_MSK_GET(GD32_REMAP_GET(pin)), 0x1, NULL);
+	zassert_equal(GD32_REMAP_VAL_GET(GD32_REMAP_GET(pin)), 1, NULL);
+	zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
+	zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
+
+	pin = scfg->pins[4];
+	zassert_equal(GD32_PORT_GET(pin), 1, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 4, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
+	zassert_equal(GD32_REMAP_REG_GET(GD32_REMAP_GET(pin)), 0, NULL);
+	zassert_equal(GD32_REMAP_POS_GET(GD32_REMAP_GET(pin)), 0, NULL);
+	zassert_equal(GD32_REMAP_MSK_GET(GD32_REMAP_GET(pin)), 0x1, NULL);
+	zassert_equal(GD32_REMAP_VAL_GET(GD32_REMAP_GET(pin)), 1, NULL);
+	zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
+
+	pin = scfg->pins[5];
+	zassert_equal(GD32_PORT_GET(pin), 2, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 5, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
+	zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
+
+	pin = scfg->pins[6];
+	zassert_equal(GD32_PORT_GET(pin), 0, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 6, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
+	zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_OD, NULL);
+
+	pin = scfg->pins[7];
+	zassert_equal(GD32_PORT_GET(pin), 1, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 7, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
+	zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
+
+	pin = scfg->pins[8];
+	zassert_equal(GD32_PORT_GET(pin), 2, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 8, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLUP, NULL);
+	zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
+
+	pin = scfg->pins[9];
+	zassert_equal(GD32_PORT_GET(pin), 0, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 9, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLDOWN, NULL);
+	zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
+
+	pin = scfg->pins[10];
+	zassert_equal(GD32_PORT_GET(pin), 1, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 10, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
+
+	pin = scfg->pins[11];
+	zassert_equal(GD32_PORT_GET(pin), 2, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 11, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_10MHZ, NULL);
+
+	pin = scfg->pins[12];
+	zassert_equal(GD32_PORT_GET(pin), 0, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 12, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_50MHZ, NULL);
+
+	pin = scfg->pins[13];
+	zassert_equal(GD32_PORT_GET(pin), 1, NULL);
+	zassert_equal(GD32_PIN_GET(pin), 13, NULL);
+	zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
+	zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
+	zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_MAX, NULL);
+}
+
+void test_main(void)
+{
+	ztest_test_suite(pinctrl_gd32,
+			 ztest_unit_test(test_dt_extract));
+	ztest_run_test_suite(pinctrl_gd32);
+}
diff --git a/tests/drivers/pinctrl/gd32/testcase.yaml b/tests/drivers/pinctrl/gd32/testcase.yaml
index 881f9c963e2..2d4e164b651 100644
--- a/tests/drivers/pinctrl/gd32/testcase.yaml
+++ b/tests/drivers/pinctrl/gd32/testcase.yaml
@@ -5,3 +5,6 @@ tests:
   drivers.pinctrl.gd32_af:
     tags: drivers pinctrl
     platform_allow: gd32f450i_eval
+  drivers.pinctrl.gd32_afio:
+    tags: drivers pinctrl
+    platform_allow: gd32f403z_eval