tests: drivers: pinctrl: gd32: add DT AFIO parse test
Add a test to check that DT information for the AFIO model is extracted correctly. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas
Anas Nashif
parent
f5ed5e6d0f
commit
1123b80aee
4 changed files with 214 additions and 0 deletions
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@ -9,4 +9,6 @@ project(pinctrl_gd32)
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target_sources(app PRIVATE ../common/test_device.c)
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if(CONFIG_PINCTRL_GD32_AF)
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target_sources(app PRIVATE src/main_af.c)
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elseif(CONFIG_PINCTRL_GD32_AFIO)
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target_sources(app PRIVATE src/main_afio.c)
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endif()
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67
tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay
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67
tests/drivers/pinctrl/gd32/boards/gd32f403z_eval.overlay
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@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define GD32_TEST_DEVICE_RMP GD32_REMAP(0, 0, 0x1U, 1)
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/ {
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test_device: test_device {
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compatible = "vnd,pinctrl-device";
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pinctrl-0 = <&test_device_default>;
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pinctrl-names = "default";
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};
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};
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&pinctrl {
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test_device_default: test_device_default {
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/* Note: the groups are just meant for testing if properties and
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pins are parsed correctly, but do not necessarily represent a
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feasible combination */
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pins1 {
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pinmux = <GD32_PINMUX_AFIO('A', 0, ANALOG, NORMP)>,
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<GD32_PINMUX_AFIO('B', 1, ALTERNATE, NORMP)>,
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<GD32_PINMUX_AFIO('C', 2, GPIO_IN, NORMP)>;
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};
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pins2 {
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pinmux = <GD32_PINMUX_AFIO('A', 3, GPIO_IN, TEST_DEVICE_RMP)>,
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<GD32_PINMUX_AFIO('B', 4, ALTERNATE, TEST_DEVICE_RMP)>;
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};
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pins3 {
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pinmux = <GD32_PINMUX_AFIO('C', 5, GPIO_IN, NORMP)>;
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drive-push-pull;
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};
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pins4 {
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pinmux = <GD32_PINMUX_AFIO('A', 6, GPIO_IN, NORMP)>;
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drive-open-drain;
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};
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pins5 {
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pinmux = <GD32_PINMUX_AFIO('B', 7, GPIO_IN, NORMP)>;
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bias-disable;
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};
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pins6 {
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pinmux = <GD32_PINMUX_AFIO('C', 8, GPIO_IN, NORMP)>;
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bias-pull-up;
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};
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pins7 {
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pinmux = <GD32_PINMUX_AFIO('A', 9, GPIO_IN, NORMP)>;
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bias-pull-down;
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};
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pins8 {
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pinmux = <GD32_PINMUX_AFIO('B', 10, ALTERNATE, NORMP)>;
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slew-rate = "max-speed-2mhz";
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};
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pins9 {
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pinmux = <GD32_PINMUX_AFIO('C', 11, ALTERNATE, NORMP)>;
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slew-rate = "max-speed-10mhz";
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};
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pins10 {
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pinmux = <GD32_PINMUX_AFIO('A', 12, ALTERNATE, NORMP)>;
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slew-rate = "max-speed-50mhz";
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};
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pins11 {
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pinmux = <GD32_PINMUX_AFIO('B', 13, ALTERNATE, NORMP)>;
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slew-rate = "max-speed-highest";
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};
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};
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};
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142
tests/drivers/pinctrl/gd32/src/main_afio.c
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142
tests/drivers/pinctrl/gd32/src/main_afio.c
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@ -0,0 +1,142 @@
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/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/pinctrl.h>
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#include <ztest.h>
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/* pin configuration for test device */
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#define TEST_DEVICE DT_NODELABEL(test_device)
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PINCTRL_DT_DEV_CONFIG_DECLARE(TEST_DEVICE);
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static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(TEST_DEVICE);
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static void test_dt_extract(void)
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{
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const struct pinctrl_state *scfg;
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pinctrl_soc_pin_t pin;
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zassert_equal(pcfg->state_cnt, 1U, NULL);
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scfg = &pcfg->states[0];
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zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT, NULL);
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zassert_equal(scfg->pin_cnt, 14U, NULL);
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pin = scfg->pins[0];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 0, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ANALOG, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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pin = scfg->pins[1];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 1, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[2];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 2, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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pin = scfg->pins[3];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 3, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
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zassert_equal(GD32_REMAP_REG_GET(GD32_REMAP_GET(pin)), 0, NULL);
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zassert_equal(GD32_REMAP_POS_GET(GD32_REMAP_GET(pin)), 0, NULL);
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zassert_equal(GD32_REMAP_MSK_GET(GD32_REMAP_GET(pin)), 0x1, NULL);
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zassert_equal(GD32_REMAP_VAL_GET(GD32_REMAP_GET(pin)), 1, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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pin = scfg->pins[4];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 4, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
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zassert_equal(GD32_REMAP_REG_GET(GD32_REMAP_GET(pin)), 0, NULL);
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zassert_equal(GD32_REMAP_POS_GET(GD32_REMAP_GET(pin)), 0, NULL);
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zassert_equal(GD32_REMAP_MSK_GET(GD32_REMAP_GET(pin)), 0x1, NULL);
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zassert_equal(GD32_REMAP_VAL_GET(GD32_REMAP_GET(pin)), 1, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[5];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 5, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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pin = scfg->pins[6];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 6, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_OD, NULL);
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pin = scfg->pins[7];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 7, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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pin = scfg->pins[8];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 8, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLUP, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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pin = scfg->pins[9];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 9, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_GPIO_IN, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLDOWN, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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pin = scfg->pins[10];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 10, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[11];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 11, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_10MHZ, NULL);
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pin = scfg->pins[12];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 12, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_50MHZ, NULL);
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pin = scfg->pins[13];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 13, NULL);
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zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE, NULL);
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zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_MAX, NULL);
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}
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void test_main(void)
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{
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ztest_test_suite(pinctrl_gd32,
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ztest_unit_test(test_dt_extract));
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ztest_run_test_suite(pinctrl_gd32);
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}
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@ -5,3 +5,6 @@ tests:
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drivers.pinctrl.gd32_af:
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tags: drivers pinctrl
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platform_allow: gd32f450i_eval
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drivers.pinctrl.gd32_afio:
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tags: drivers pinctrl
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platform_allow: gd32f403z_eval
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