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Merge "Merge arm branch into master"

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Anas Nashif 2017-02-11 04:00:58 +00:00
commit 110df98619
58 changed files with 1532 additions and 2977 deletions
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2
include/arch/arm/arch.h
View file

@ -36,8 +36,6 @@ extern "C" {
#include <arch/arm/cortex_m/irq.h>
#include <arch/arm/cortex_m/error.h>
#include <arch/arm/cortex_m/misc.h>
#include <arch/arm/cortex_m/scs.h>
#include <arch/arm/cortex_m/scb.h>
#include <arch/arm/cortex_m/memory_map.h>
#include <arch/arm/cortex_m/asm_inline.h>
#include <arch/arm/cortex_m/addr_types.h>

69
include/arch/arm/cortex_m/cmsis.h
View file

@ -22,19 +22,68 @@ extern "C" {
/* CP10 Access Bits */
#define CPACR_CP10_Pos 20U
#define CPACR_CP10_Msk (3UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_NO_ACCESS (0UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_PRIV_ACCESS (1UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_RESERVED (2UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_FULL_ACCESS (3UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_Msk (3UL << CPACR_CP10_Pos)
#define CPACR_CP10_NO_ACCESS (0UL << CPACR_CP10_Pos)
#define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos)
#define CPACR_CP10_RESERVED (2UL << CPACR_CP10_Pos)
#define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos)
/* CP11 Access Bits */
#define CPACR_CP11_Pos 22U
#define CPACR_CP11_Msk (3UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_NO_ACCESS (0UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_PRIV_ACCESS (1UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_RESERVED (2UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_FULL_ACCESS (3UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_Msk (3UL << CPACR_CP11_Pos)
#define CPACR_CP11_NO_ACCESS (0UL << CPACR_CP11_Pos)
#define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos)
#define CPACR_CP11_RESERVED (2UL << CPACR_CP11_Pos)
#define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos)
#define SCB_UFSR (*((__IOM uint16_t *) &SCB->CFSR + 2))
#define SCB_BFSR (*((__IOM uint8_t *) &SCB->CFSR + 1))
#define SCB_MMFSR (*((__IOM uint8_t *) &SCB->CFSR))
/* CFSR[UFSR] */
#define CFSR_DIVBYZERO_Pos (25U)
#define CFSR_DIVBYZERO_Msk (0x1U << CFSR_DIVBYZERO_Pos)
#define CFSR_UNALIGNED_Pos (24U)
#define CFSR_UNALIGNED_Msk (0x1U << CFSR_UNALIGNED_Pos)
#define CFSR_NOCP_Pos (19U)
#define CFSR_NOCP_Msk (0x1U << CFSR_NOCP_Pos)
#define CFSR_INVPC_Pos (18U)
#define CFSR_INVPC_Msk (0x1U << CFSR_INVPC_Pos)
#define CFSR_INVSTATE_Pos (17U)
#define CFSR_INVSTATE_Msk (0x1U << CFSR_INVSTATE_Pos)
#define CFSR_UNDEFINSTR_Pos (16U)
#define CFSR_UNDEFINSTR_Msk (0x1U << CFSR_UNDEFINSTR_Pos)
/* CFSR[BFSR] */
#define CFSR_BFARVALID_Pos (15U)
#define CFSR_BFARVALID_Msk (0x1U << CFSR_BFARVALID_Pos)
#define CFSR_LSPERR_Pos (13U)
#define CFSR_LSPERR_Msk (0x1U << CFSR_LSPERR_Pos)
#define CFSR_STKERR_Pos (12U)
#define CFSR_STKERR_Msk (0x1U << CFSR_STKERR_Pos)
#define CFSR_UNSTKERR_Pos (11U)
#define CFSR_UNSTKERR_Msk (0x1U << CFSR_UNSTKERR_Pos)
#define CFSR_IMPRECISERR_Pos (10U)
#define CFSR_IMPRECISERR_Msk (0x1U << CFSR_IMPRECISERR_Pos)
#define CFSR_PRECISERR_Pos (9U)
#define CFSR_PRECISERR_Msk (0x1U << CFSR_PRECISERR_Pos)
#define CFSR_IBUSERR_Pos (8U)
#define CFSR_IBUSERR_Msk (0x1U << CFSR_IBUSERR_Pos)
/* CFSR[MMFSR] */
#define CFSR_MMARVALID_Pos (7U)
#define CFSR_MMARVALID_Msk (0x1U << CFSR_MMARVALID_Pos)
#define CFSR_MLSPERR_Pos (5U)
#define CFSR_MLSPERR_Msk (0x1U << CFSR_MLSPERR_Pos)
#define CFSR_MSTKERR_Pos (4U)
#define CFSR_MSTKERR_Msk (0x1U << CFSR_MSTKERR_Pos)
#define CFSR_MUNSTKERR_Pos (3U)
#define CFSR_MUNSTKERR_Msk (0x1U << CFSR_MUNSTKERR_Pos)
#define CFSR_DACCVIOL_Pos (1U)
#define CFSR_DACCVIOL_Msk (0x1U << CFSR_DACCVIOL_Pos)
#define CFSR_IACCVIOL_Pos (0U)
#define CFSR_IACCVIOL_Msk (0x1U << CFSR_IACCVIOL_Pos)
/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
* Use __NVIC_PRIO_BITS as it is required and simple to check, but

583
include/arch/arm/cortex_m/scb.h
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@ -1,583 +0,0 @@
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM CORTEX-M System Control Block interface
*
* Provide an interface to the System Control Block found on ARM Cortex-M
* processors.
*
* The API does not account for all possible usages of the SCB, only the
* functionalities needed by the kernel. It does not contain NVIC
* functionalities either: these can be found in nvic.h. MPU functionalities
* are not implemented.
*
* The same effect can be achieved by directly writing in the registers of the
* SCB, with the layout available from scs.h, using the __scs.scb data
* structure (or hardcoded values), but the APIs found here are less
* error-prone, especially for registers with multiple instances to account
* for 16 exceptions.
*
* If access to a missing functionality is needed, directly writing to the
* registers is the way to implement it.
*/
#ifndef _SCB__H_
#define _SCB__H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#else
#include <kernel.h>
#include <arch/cpu.h>
#include <misc/__assert.h>
#include <arch/arm/cortex_m/scs.h>
#include <misc/util.h>
#include <stdint.h>
/**
*
* @brief Obtain the currently executing vector
*
* If currently handling an exception/interrupt, return the executing vector
* number. If not, return 0.
*
* @return the currently executing vector number, 0 if in thread mode.
*/
static inline uint32_t _ScbActiveVectorGet(void)
{
return __scs.scb.icsr.bit.vectactive;
}
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Find out if the currently executing exception is nested
*
* This routine determines if the currently executing exception is nested.
*
* @return 1 if nested, 0 otherwise
*/
static inline int _ScbIsNestedExc(void)
{
/* !bit == preempted exceptions */
return !__scs.scb.icsr.bit.rettobase;
}
/**
*
* @brief Enable faulting on division by zero
*
* This routine enables the divide by zero fault.
* By default, the CPU ignores the error.
*
* @return N/A
*/
static inline void _ScbDivByZeroFaultEnable(void)
{
__scs.scb.ccr.bit.div_0_trp = 1;
}
/**
*
* @brief Enable usage fault exceptions
*
* This routine enables usage faults.
* By default, the CPU does not raise usage fault exceptions.
*
* @return N/A
*/
static inline void _ScbUsageFaultEnable(void)
{
__scs.scb.shcsr.bit.usgfaultena = 1;
}
/**
*
* @brief Enable bus fault exceptions
*
* This routine enables bus faults.
* By default, the CPU does not raise bus fault exceptions.
*
* @return N/A
*/
static inline void _ScbBusFaultEnable(void)
{
__scs.scb.shcsr.bit.busfaultena = 1;
}
/**
*
* @brief Enable MPU faults exceptions
*
* This routine enables the MPU faults.
* By default, the CPU does not raise MPU fault exceptions.
*
* @return N/A
*/
static inline void _ScbMemFaultEnable(void)
{
__scs.scb.shcsr.bit.memfaultena = 1;
}
/**
*
* @brief Find out if a hard fault is caused by a bus error on vector read
*
* This routine determines if a hard fault is caused by a bus error during
* a vector table read operation.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbHardFaultIsBusErrOnVectorRead(void)
{
return __scs.scb.hfsr.bit.vecttbl;
}
/**
*
* @brief Find out if a fault was escalated to hard fault
*
* Happens if a fault cannot be triggered because of priority or because it was
* disabled.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbHardFaultIsForced(void)
{
return __scs.scb.hfsr.bit.forced;
}
/**
*
* @brief Clear all hard faults (HFSR register)
*
* HFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbHardFaultAllFaultsReset(void)
{
return __scs.scb.hfsr.val = 0xffff;
}
/**
*
* @brief Find out if a hard fault is an MPU fault
*
* This routine determines if a hard fault is an MPU fault.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbIsMemFault(void)
{
return !!__scs.scb.cfsr.byte.mmfsr.val;
}
/**
*
* @brief Find out if the MMFAR register contains a valid value
*
* The MMFAR register contains the faulting address on an MPU fault.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsMmfarValid(void)
{
return !!__scs.scb.cfsr.byte.mmfsr.bit.mmarvalid;
}
/**
*
* @brief Invalid the value in MMFAR
*
* This routine invalidates the MMFAR value. This should be done after
* processing an MPU fault.
*
* @return N/A
*/
static inline void _ScbMemFaultMmfarReset(void)
{
__scs.scb.cfsr.byte.mmfsr.bit.mmarvalid = 0;
}
/**
*
* @brief Clear all MPU faults (MMFSR register)
*
* CFSR/MMFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return 1 if so, 0 otherwise
*/
static inline void _ScbMemFaultAllFaultsReset(void)
{
__scs.scb.cfsr.byte.mmfsr.val = 0xfe;
}
/**
*
* @brief Find out if an MPU fault is a stacking fault
*
* This routine determines if an MPU fault is a stacking fault.
* This may occur upon exception entry.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsStacking(void)
{
return !!__scs.scb.cfsr.byte.mmfsr.bit.mstkerr;
}
/**
*
* @brief Find out if an MPU fault is an unstacking fault
*
* This routine determines if an MPU fault is an unstacking fault.
* This may occur upon exception exit.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsUnstacking(void)
{
return !!__scs.scb.cfsr.byte.mmfsr.bit.munstkerr;
}
/**
*
* @brief Find out if an MPU fault is a data access violation
*
* If this routine returns 1, read the MMFAR register via _ScbMemFaultAddrGet()
* to get the faulting address.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsDataAccessViolation(void)
{
return !!__scs.scb.cfsr.byte.mmfsr.bit.daccviol;
}
/**
*
* @brief Find out if an MPU fault is an instruction access violation
*
* This routine determines if an MPU fault is due to an instruction access
* violation.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbMemFaultIsInstrAccessViolation(void)
{
return !!__scs.scb.cfsr.byte.mmfsr.bit.iaccviol;
}
/**
*
* @brief Find out the faulting address on an MPU fault
*
* @return the faulting address
*/
static inline uint32_t _ScbMemFaultAddrGet(void)
{
return __scs.scb.mmfar;
}
/**
*
* @brief Find out if a hard fault is a bus fault
*
* This routine determines if a hard fault is a bus fault.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbIsBusFault(void)
{
return !!__scs.scb.cfsr.byte.bfsr.val;
}
/**
*
* @brief Find out if the BFAR register contains a valid value
*
* The BFAR register contains the faulting address on bus fault.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsBfarValid(void)
{
return !!__scs.scb.cfsr.byte.bfsr.bit.bfarvalid;
}
/**
*
* @brief Invalid the value in BFAR
*
* This routine clears/invalidates the Bus Fault Address Register.
* It should be done after processing a bus fault.
*
* @return N/A
*/
static inline void _ScbBusFaultBfarReset(void)
{
__scs.scb.cfsr.byte.bfsr.bit.bfarvalid = 0;
}
/**
*
* @brief Clear all bus faults (BFSR register)
*
* CFSR/BFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return N/A
*/
static inline void _ScbBusFaultAllFaultsReset(void)
{
__scs.scb.cfsr.byte.bfsr.val = 0xfe;
}
/**
*
* @brief Find out if a bus fault is a stacking fault
*
* This routine determines if a bus fault is a stacking fault.
* This may occurs upon exception entry.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsStacking(void)
{
return !!__scs.scb.cfsr.byte.bfsr.bit.stkerr;
}
/**
*
* @brief Find out if a bus fault is an unstacking fault
*
* This routine determines if a bus fault is an unstacking fault.
* This may occur upon exception exit.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsUnstacking(void)
{
return !!__scs.scb.cfsr.byte.bfsr.bit.unstkerr;
}
/**
*
* @brief Find out if a bus fault is an imprecise error
*
* This routine determines if a bus fault is an imprecise error.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsImprecise(void)
{
return !!__scs.scb.cfsr.byte.bfsr.bit.impreciserr;
}
/**
*
* @brief Find out if a bus fault is an precise error
*
* Read the BFAR register via _ScbBusFaultAddrGet() if this routine returns 1,
* as it will contain the faulting address.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsPrecise(void)
{
return !!__scs.scb.cfsr.byte.bfsr.bit.preciserr;
}
/**
*
* @brief Find out if a bus fault is an instruction bus error
*
* This routine determines if a bus fault is an instruction bus error.
* It is signalled only if the instruction is issued.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbBusFaultIsInstrBusErr(void)
{
return !!__scs.scb.cfsr.byte.bfsr.bit.ibuserr;
}
/**
*
* @brief Get the faulting address on a precise bus fault
*
* This routine returns the faulting address for a precise bus fault.
*
* @return the faulting address
*/
static inline uint32_t _ScbBusFaultAddrGet(void)
{
return __scs.scb.bfar;
}
/**
*
* @brief Find out if a hard fault is a usage fault
*
* This routine determines if a hard fault is a usage fault.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbIsUsageFault(void)
{
return !!__scs.scb.cfsr.byte.ufsr.val;
}
/**
*
* @brief Find out if a usage fault is a 'divide by zero' fault
*
* This routine determines if a usage fault is a 'divide by zero' fault.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsDivByZero(void)
{
return !!__scs.scb.cfsr.byte.ufsr.bit.divbyzero;
}
/**
*
* @brief Find out if a usage fault is a unaligned access error
*
* This routine determines if a usage fault is an unaligned access error.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsUnaligned(void)
{
return !!__scs.scb.cfsr.byte.ufsr.bit.unaligned;
}
/**
*
* @brief Find out if a usage fault is a co-processor access error
*
* This routine determines if a usage fault is caused by a co-processor access.
* This happens if the co-processor is either absent or disabled.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsNoCp(void)
{
return !!__scs.scb.cfsr.byte.ufsr.bit.nocp;
}
/**
*
* @brief Find out if a usage fault is a invalid PC load error
*
* Happens if the the instruction address on an exception return is not
* halfword-aligned.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsInvalidPcLoad(void)
{
return !!__scs.scb.cfsr.byte.ufsr.bit.invpc;
}
/**
*
* @brief Find out if a usage fault is a invalid state error
*
* Happens if the the instruction address loaded in the PC via a branch, LDR or
* POP, or if the instruction address installed in a exception vector, does not
* have bit 0 set; i.e, is not halfword-aligned.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsInvalidState(void)
{
return !!__scs.scb.cfsr.byte.ufsr.bit.invstate;
}
/**
*
* @brief Find out if a usage fault is a undefined instruction error
*
* The processor tried to execute an invalid opcode.
*
* @return 1 if so, 0 otherwise
*/
static inline int _ScbUsageFaultIsUndefinedInstr(void)
{
return !!__scs.scb.cfsr.byte.ufsr.bit.undefinstr;
}
/**
*
* @brief Clear all usage faults (UFSR register)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return N/A
*/
static inline void _ScbUsageFaultAllFaultsReset(void)
{
__scs.scb.cfsr.byte.ufsr.val = 0xffff;
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* _SCB__H_ */

598
include/arch/arm/cortex_m/scs.h
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@ -1,598 +0,0 @@
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM CORTEX-M System Control Space
*
* Define the System Control Space for the CORTEX-M series of processors and
* provide an interface for miscellaneous SCS functionalities.
*
* All register and bit-field names come from the
*
* Cortex-M3 Devices
* Generic User Guide
* ARM DUI 0552A (ID121610)
*
* and
*
* Cortex-M3
* Revision r2p1
* Technical Reference Manual
* ARM DDI 0337I (ID072410)
*
* documents from ARM.
*
* The API does not account for all possible usages of the SCS, only the
* functionalities needed by the kernel. It does not contain NVIC and
* SCB functionalities either: these can be found in nvic.h and scb.h.
*
* MPU functionalities are not implemented.
*
* The same effect can be achieved by directly writing in the registers of the
* SCS, using the __scs data structure (or hardcoded values), but the APIs found
* here are less error-prone, especially for registers with multiple instances
* to account for 16 exceptions.
*
* If access to a missing functionality is needed, directly writing to the
* registers is the way to implement it.
*
* Note that the 'stir' register, even if not in the 'nvic' part of the SCB, is
* still considered part of the NVIC and an API for it is provided in nvic.h.
*/
#ifndef _SCS__H_
#define _SCS__H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#include <arch/arm/cortex_m/memory_map.h>
#else /* _ASMLANGUAGE */
#include <kernel.h>
#include <arch/cpu.h>
#include <stdint.h>
union __ictr {
uint32_t val;
struct {
uint32_t intlinesnum : 4 __packed;
uint32_t rsvd__4_31 : 28 __packed;
} bit;
};
union __actlr {
uint32_t val;
struct {
uint32_t dismcycint : 1 __packed;
uint32_t disdefwbuf : 1 __packed;
uint32_t disfold : 1 __packed;
uint32_t rsvd__3_31 : 28 __packed;
} bit;
};
union __stcsr {
uint32_t val;
struct {
uint8_t enable : 1 __packed;
uint8_t tickint : 1 __packed;
uint8_t clksource : 1 __packed;
uint16_t rsvd__3_15 : 13 __packed;
uint16_t countflag : 1 __packed;
uint16_t rsvd__17_31 : 15 __packed;
} bit;
};
union __cpuid {
uint32_t val;
struct {
uint32_t revision : 4 __packed;
uint32_t partno : 12 __packed;
uint32_t constant : 4 __packed;
uint32_t variant : 4 __packed;
uint32_t implementer : 8 __packed;
} bit;
};
union __icsr {
uint32_t val;
struct {
#if defined(CONFIG_ARMV6_M)
uint32_t vectactive : 9 __packed;
uint32_t rsvd__9_10_11 : 3 __packed;
uint32_t vectpending : 9 __packed;
uint32_t rsvd__21 : 1 __packed;
#elif defined(CONFIG_ARMV7_M)
uint32_t vectactive : 10 __packed;
uint32_t rsvd__10 : 1 __packed;
uint32_t rettobase : 1 __packed;
uint32_t vectpending : 10 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
uint32_t isrpending : 1 __packed;
uint32_t rsvd__23 : 1 __packed;
uint32_t rsvd__24 : 1 __packed;
uint32_t pendstclr : 1 __packed;
uint32_t pendstset : 1 __packed;
uint32_t pendsvclr : 1 __packed;
uint32_t pendsvset : 1 __packed;
uint32_t rsvd__29_30 : 2 __packed;
uint32_t nmipendset : 1 __packed;
} bit;
};
union __vtor {
uint32_t val;
struct {
uint32_t rsvd__0_6 : 7 __packed;
uint32_t tbloff : 22 __packed;
uint32_t tblbase : 1 __packed;
uint32_t rsvd__30_31 : 2 __packed;
} bit;
};
union __aircr {
uint32_t val;
struct {
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd__0 : 1 __packed;
#elif defined(CONFIG_ARMV7_M)
uint32_t vecreset : 1 __packed; /* WO */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
uint32_t vectclractive : 1 __packed; /* WO */
uint32_t sysresetreq : 1 __packed; /* WO */
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd__3_14 : 12 __packed;
#elif defined(CONFIG_ARMV7_M)
uint32_t rsvd__3_7 : 5 __packed;
uint32_t prigroup : 3 __packed;
uint32_t rsvd__11_14 : 4 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
uint32_t endianness : 1 __packed; /* RO */
uint32_t vectkey : 16 __packed;
} bit;
};
union __scr {
uint32_t val;
struct {
uint32_t rsvd__0 : 1 __packed;
uint32_t sleeponexit : 1 __packed;
uint32_t sleepdeep : 1 __packed;
uint32_t rsvd__3 : 1 __packed;
uint32_t sevonpend : 1 __packed;
uint32_t rsvd__5_31 : 27 __packed;
} bit;
};
#define _SCB_CCR_DIV_0_TRP (1 << 4)
#define _SCB_CCR_UNALIGN_TRP (1 << 3)
union __ccr {
uint32_t val;
struct {
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_0_2 : 3 __packed;
#elif defined(CONFIG_ARMV7_M)
uint32_t nonbasethrdena : 1 __packed;
uint32_t usersetmpend : 1 __packed;
uint32_t rsvd__2 : 1 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
uint32_t unalign_trp : 1 __packed;
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_4_8 : 5 __packed;
#elif defined(CONFIG_ARMV7_M)
uint32_t div_0_trp : 1 __packed;
uint32_t rsvd__5_7 : 3 __packed;
uint32_t bfhfnmign : 1 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
uint32_t stkalign : 1 __packed;
uint32_t rsvd__10_31 : 22 __packed;
} bit;
};
union __shcsr {
uint32_t val;
struct {
uint32_t memfaultact : 1 __packed;
uint32_t busfaultact : 1 __packed;
uint32_t rsvd__2 : 1 __packed;
uint32_t usgfaultact : 1 __packed;
uint32_t rsvd__4_6 : 3 __packed;
uint32_t svcallact : 1 __packed;
uint32_t monitoract : 1 __packed;
uint32_t rsvd__9 : 1 __packed;
uint32_t pendsvact : 1 __packed;
uint32_t systickact : 1 __packed;
uint32_t usgfaultpended : 1 __packed;
uint32_t memfaultpended : 1 __packed;
uint32_t busfaultpended : 1 __packed;
uint32_t svcallpended : 1 __packed;
uint32_t memfaultena : 1 __packed;
uint32_t busfaultena : 1 __packed;
uint32_t usgfaultena : 1 __packed;
uint32_t rsvd__19_31 : 13 __packed;
} bit;
};
union __cfsr {
uint32_t val;
struct {
union {
uint8_t val;
struct {
uint8_t iaccviol : 1 __packed;
uint8_t daccviol : 1 __packed;
uint8_t rsvd__2 : 1 __packed;
uint8_t munstkerr : 1 __packed;
uint8_t mstkerr : 1 __packed;
uint8_t rsvd__5_6 : 2 __packed;
uint8_t mmarvalid : 1 __packed;
} bit;
} mmfsr;
union {
uint8_t val;
struct {
uint8_t ibuserr : 1 __packed;
uint8_t preciserr : 1 __packed;
uint8_t impreciserr : 1 __packed;
uint8_t unstkerr : 1 __packed;
uint8_t stkerr : 1 __packed;
uint8_t rsvd__5_6 : 2 __packed;
uint8_t bfarvalid : 1 __packed;
} bit;
} bfsr;
union {
uint16_t val;
struct {
uint16_t undefinstr : 1 __packed;
uint16_t invstate : 1 __packed;
uint16_t invpc : 1 __packed;
uint16_t nocp : 1 __packed;
uint16_t rsvd__4_7 : 4 __packed;
uint16_t unaligned : 1 __packed;
uint16_t divbyzero : 1 __packed;
uint16_t rsvd__10_15 : 6 __packed;
} bit;
} ufsr;
} byte;
};
union __hfsr {
uint32_t val;
struct {
uint32_t rsvd__0 : 1 __packed;
uint32_t vecttbl : 1 __packed;
uint32_t rsvd__2_29 : 28 __packed;
uint32_t forced : 1 __packed;
uint32_t debugevt : 1 __packed;
} bit;
};
union __mpu_type {
uint32_t val;
struct {
uint32_t separate : 1 __packed;
uint32_t rsvd__1_7 : 7 __packed;
uint32_t dregion : 8 __packed;
uint32_t iregion : 8 __packed;
uint32_t rsvd__24_31 : 8 __packed;
} bit;
};
union __mpu_ctrl {
uint32_t val;
struct {
uint32_t enable : 1 __packed;
uint32_t hfnmiena : 1 __packed;
uint32_t privdefena : 1 __packed;
uint32_t rsvd__24_31 : 29 __packed;
} bit;
};
union __mpu_rnr {
uint32_t val;
struct {
uint32_t region : 8 __packed;
uint32_t rsvd__24_31 : 24 __packed;
} bit;
};
union __mpu_rbar {
uint32_t val;
struct {
uint8_t region : 4 __packed;
uint8_t valid : 1 __packed;
uint32_t addr : 27 __packed;
} bit;
};
union __mpu_rasr {
uint32_t val;
struct {
uint32_t enable : 1 __packed;
uint32_t size : 5 __packed;
uint32_t rsvd__6_7 : 2 __packed;
uint32_t srd : 8 __packed;
uint32_t b : 1 __packed;
uint32_t c : 1 __packed;
uint32_t s : 1 __packed;
uint32_t tex : 3 __packed;
uint32_t rsvd__22_23 : 2 __packed;
uint32_t ap : 3 __packed;
uint32_t rsvd__27 : 1 __packed;
uint32_t xn : 1 __packed;
uint32_t rsvd__29_31 : 3 __packed;
} bit;
};
union __cpacr { /* Coprocessor Access Control Register */
uint32_t val;
struct {
uint32_t rsvd__0_19 : 20 __packed;
uint32_t cp10 : 2 __packed;
uint32_t cp11 : 2 __packed;
uint32_t rsvd__24_31 : 8 __packed;
} bit;
};
/* CP10 Access Bits */
#define _SCS_CPACR_CP10_Pos 20U
#define _SCS_CPACR_CP10_Msk (3UL << _SCS_CPACR_CP10_Pos)
#define _SCS_CPACR_CP10_NO_ACCESS (0UL << _SCS_CPACR_CP10_Pos)
#define _SCS_CPACR_CP10_PRIV_ACCESS (1UL << _SCS_CPACR_CP10_Pos)
#define _SCS_CPACR_CP10_RESERVED (2UL << _SCS_CPACR_CP10_Pos)
#define _SCS_CPACR_CP10_FULL_ACCESS (3UL << _SCS_CPACR_CP10_Pos)
/* CP11 Access Bits */
#define _SCS_CPACR_CP11_Pos 22U
#define _SCS_CPACR_CP11_Msk (3UL << _SCS_CPACR_CP11_Pos)
#define _SCS_CPACR_CP11_NO_ACCESS (0UL << _SCS_CPACR_CP11_Pos)
#define _SCS_CPACR_CP11_PRIV_ACCESS (1UL << _SCS_CPACR_CP11_Pos)
#define _SCS_CPACR_CP11_RESERVED (2UL << _SCS_CPACR_CP11_Pos)
#define _SCS_CPACR_CP11_FULL_ACCESS (3UL << _SCS_CPACR_CP11_Pos)
union __fpu_ccr { /* FPU Context Control Register */
uint32_t val;
struct {
uint32_t lspact : 1 __packed;
uint32_t user : 1 __packed;
uint32_t rsvd__2 : 1 __packed;
uint32_t thread : 1 __packed;
uint32_t hfrdy : 1 __packed;
uint32_t mmrdy : 1 __packed;
uint32_t bfrdy : 1 __packed;
uint32_t rsvd__7 : 1 __packed;
uint32_t monrdy : 1 __packed;
uint32_t rsvd__9_29 : 21 __packed;
uint32_t lspen : 1 __packed;
uint32_t aspen : 1 __packed;
} bit;
};
#define _SCS_FPU_CCR_ASPEN_Pos 31U
#define _SCS_FPU_CCR_ASPEN_Msk (1UL << _SCS_FPU_CCR_ASPEN_Pos)
#define _SCS_FPU_CCR_ASPEN_ENABLE (1UL << _SCS_FPU_CCR_ASPEN_Pos)
#define _SCS_FPU_CCR_ASPEN_DISABLE (0UL << _SCS_FPU_CCR_ASPEN_Pos)
#define _SCS_FPU_CCR_LSPEN_Pos 30U
#define _SCS_FPU_CCR_LSPEN_Msk (1UL << _SCS_FPU_CCR_LSPEN_Pos)
#define _SCS_FPU_CCR_LSPEN_ENABLE (1UL << _SCS_FPU_CCR_LSPEN_Pos)
#define _SCS_FPU_CCR_LSPEN_DISABLE (0UL << _SCS_FPU_CCR_LSPEN_Pos)
union __fpu_car { /* FPU Context Address Register */
uint32_t val;
struct {
uint32_t rsvd__0_2 : 3 __packed;
uint32_t address : 29 __packed;
} bit;
};
union __fpu_scr { /* FPU Status Control Register */
uint32_t val;
struct {
uint32_t ioc : 1 __packed;
uint32_t dzc : 1 __packed;
uint32_t ofc : 1 __packed;
uint32_t ufc : 1 __packed;
uint32_t ixc : 1 __packed;
uint32_t rsvd__5_6 : 2 __packed;
uint32_t idc : 1 __packed;
uint32_t rsvd__8_21 : 14 __packed;
uint32_t rmode : 2 __packed;
uint32_t fz : 1 __packed;
uint32_t dn : 1 __packed;
uint32_t ahp : 1 __packed;
uint32_t rsvd__27 : 1 __packed;
uint32_t v : 1 __packed;
uint32_t c : 1 __packed;
uint32_t z : 1 __packed;
uint32_t n : 1 __packed;
} bit;
};
union __fpu_dscr { /* FPU Default Status Control Register */
uint32_t val;
struct {
uint32_t rsvd__0_21 : 22 __packed;
uint32_t rmode : 2 __packed;
uint32_t fz : 1 __packed;
uint32_t dn : 1 __packed;
uint32_t ahp : 1 __packed;
uint32_t rsvd__27_31 : 5 __packed;
} bit;
};
struct __scs {
uint32_t rsvd__MasterControlRegister;
union __ictr ictr; /* 0x004 Interrupt Controller Type Register */
union __actlr actlr; /* 0x008 Auxiliary ConTroL Register */
uint32_t rsvd__00c_00f;
/* system ticker (SYSTICK) */
struct {
union __stcsr stcsr; /* 0x10 Control and Status Register */
uint32_t strvr; /* 0x14 Reload Value Register (low 24 bits) */
uint32_t stcvr; /* 0x18 Current Value Register (low 24 bits) */
uint32_t stcr; /* 0x1c Calibration value Register */
} systick; /* offset: 0x010, size 0x10 */
uint32_t rsvd__020_0ff[(0x100 - 0x20) / 4];
/* Nested Vector Interrupt Controller (NVIC)
*
* Each block of 8 32-bit words could in theory support 256 IRQs, but
* the architecture only supports IRQs 0 -> 239.
*/
struct {
uint32_t iser[8]; /* 0x100 Interrupt Set-Enable Registers */
uint32_t rsvd__120_17f[24];
uint32_t icer[8]; /* 0x180 Interrupt Clear-Enable Registers */
uint32_t rsvd__1a0_1ff[24];
uint32_t ispr[8]; /* 0x200 Interrupt Set-Pending Registers */
uint32_t rsvd__220_27f[24];
uint32_t icpr[8]; /* 0x280 Interrupt Clear-Pending Registers */
uint32_t rsvd__2a0_2ff[24];
uint32_t iabr[8]; /* 0x300 Interrupt Active-Bit Registers */
uint32_t rsvd__320_37f[24];
uint32_t rsvd__380_3ff[32];
#if defined(CONFIG_ARMV6_M)
uint32_t ipr[8];
uint32_t rsvd__420_4ff[56];
#elif defined(CONFIG_ARMV7_M)
uint8_t ipr[240]; /* 0x400 Interrupt Priority Registers */
uint32_t rsvd__4f0_4ff[4];
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
} nvic; /* offset: 0x100, size 0x400 */
uint32_t rsvd__500_cff[(0xd00 - 0x500) / 4];
/* System Control Block (SCB) */
struct {
union __cpuid cpuid; /* 0xd00 CPUID register */
union __icsr icsr; /* 0xd04 IRQ Control and Start Register */
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_9_12;
#elif defined(CONFIG_ARMV7_M)
union __vtor vtor; /* 0xd08 Vector Table Offset Register */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
union __aircr
aircr; /* 0xd0c App IRQ and Reset Control Register */
union __scr scr; /* 0xd10 System Control Register */
union __ccr ccr; /* 0xd14 Configuration and Control Register */
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_24_27;
uint32_t shpr[2];
#elif defined(CONFIG_ARMV7_M)
uint8_t shpr[12]; /* 0xd18 System Handler Priority Registers
* Use ('exception number' - 4) to
* get index into array
*/
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
union __shcsr
shcsr; /* 0xd24 Sys Handler Control and State Reg */
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_40_63[6];
#elif defined(CONFIG_ARMV7_M)
union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register
*/
union __hfsr hfsr; /* 0xd2C Hard Fault Status Register */
uint32_t dfsr; /* 0xd30 Debug Fault Status Register */
uint32_t mmfar; /* 0xd34 MemManage Fault Address Register */
uint32_t bfar; /* 0xd38 BusFault Address Register */
uint32_t afsr; /* 0xd3C Aux Fault Status Register */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
} scb; /* offset: 0xd00, size 0x040 */
/*
* d40 -> d7f: processor feature ID registers (pp.778-779 in DDI0403D)
*/
uint32_t rsvd__d40_d87[(0xd88 - 0xd40) / 4];
union __cpacr cpacr; /* 0xd88 Coprocessor Access Control Reg */
uint32_t rsvd__d8c_d8f;
/* Memory Protection Unit (MPU) */
struct { /* 0xD90-0xDA3 */
union __mpu_type mpu_type; /* 0xd90 RO TYPE register */
union __mpu_ctrl mpu_ctrl; /* 0xd94 RW ConTRoL register */
union __mpu_rnr mpu_rnr; /* 0xd98 RW Region Number Register */
union __mpu_rbar mpu_rbar; /* 0xd9c RW Region Base Addr Reg. */
union __mpu_rasr mpu_rasr; /* 0xda0 RW Region Attr and Size
* Reg.
*/
union __mpu_rbar mpu_rbar_a1; /* 0xda4 RW alias of mpu_rbar */
union __mpu_rasr mpu_rasr_a1; /* 0xda8 RW alias of mpu_rasr */
union __mpu_rbar mpu_rbar_a2; /* 0xdac RW alias of mpu_rbar */
union __mpu_rasr mpu_rasr_a2; /* 0xdb0 RW alias of mpu_rasr */
union __mpu_rbar mpu_rbar_a3; /* 0xdb4 RW alias of mpu_rbar */
union __mpu_rasr mpu_rasr_a3; /* 0xdb8 RW alias of mpu_rasr */
} mpu; /* offset: 0xd90, size: 0x02c */
uint32_t rsvd__da4_eff[(0xf00 - 0xdbc) / 4];
/* 0xf00 WO SW Trigger IRQ Reg. (bit 0-8/IRQ 0-239 only) */
uint32_t stir;
uint32_t rsvd__f04_f33[(0xf34 - 0xF04) / 4];
struct { /* 0xF34-F3F */
union __fpu_ccr ccr; /* 0xf34 Context Control Reg */
union __fpu_car car; /* 0xf38 Context Address Reg */
union __fpu_dscr dscr; /* 0xf3c Default Status Control Reg */
} fpu; /* offset: 0xf34, size: 0x0c */
uint32_t rsvd__f40_fff[(0x1000 - 0xf40) / 4];
};
/* the linker always puts this object at 0xe000e000 */
extern volatile struct __scs __scs;
#if defined(CONFIG_ARMV6_M)
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and masks */
#define _PRIO_BIT_SHIFT(IRQn) (((((uint32_t)(IRQn))) & 0x03UL) * 8UL)
#define _PRIO_SHP_IDX(IRQn) ((((((uint32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL))
#define _PRIO_IP_IDX(IRQn) ((((uint32_t)(IRQn)) >> 2UL))
#elif defined(CONFIG_ARMV7_M)
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* _SCS__H_ */