Merge "Merge arm branch into master"
This commit is contained in:
Anas Nashif
commit
110df98619
58 changed files with 1532 additions and 2977 deletions
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@ -6,6 +6,6 @@ ccflags-y +=-I$(srctree)/include/
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asflags-y = $(ccflags-y)
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obj-y = vector_table.o reset.o \
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nmi_on_reset.o prep_c.o scs.o scb.o nmi.o \
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nmi_on_reset.o prep_c.o scb.o nmi.o \
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exc_manage.o
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@ -1,22 +0,0 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM CORTEX-M Series System Control Space
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*
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* Most of the SCS interface consists of simple bit-flipping methods, and is
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* implemented as inline functions in scs.h. This module thus contains only data
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* definitions and more complex routines, if needed.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <toolchain.h>
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#include <sections.h>
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/* the linker always puts this object at 0xe000e000 */
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volatile struct __scs __scs_section __scs;
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@ -64,33 +64,32 @@ void _FaultDump(const NANO_ESF *esf, int fault)
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int escalation = 0;
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if (3 == fault) { /* hard fault */
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escalation = _ScbHardFaultIsForced();
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escalation = SCB->HFSR & SCB_HFSR_FORCED_Msk;
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PR_EXC("HARD FAULT: %s\n",
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escalation ? "Escalation (see below)!"
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: "Bus fault on vector table read\n");
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}
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PR_EXC("MMFSR: 0x%" PRIx32 ", BFSR: 0x%" PRIx32 ", UFSR: 0x%"
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PRIx32 "\n",
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__scs.scb.cfsr.byte.mmfsr.val,
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__scs.scb.cfsr.byte.bfsr.val,
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__scs.scb.cfsr.byte.ufsr.val);
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PRIx32 "\n", SCB_MMFSR, SCB_BFSR, SCB_MMFSR);
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if (_ScbMemFaultIsMmfarValid()) {
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PR_EXC("MMFAR: 0x%" PRIx32 "\n", _ScbMemFaultAddrGet());
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if (SCB->CFSR & CFSR_MMARVALID_Msk) {
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PR_EXC("MMFAR: 0x%" PRIx32 "\n", SCB->MMFAR);
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if (escalation) {
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_ScbMemFaultMmfarReset();
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/* clear MMAR[VALID] to reset */
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SCB->CFSR &= ~CFSR_MMARVALID_Msk;
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}
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}
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if (_ScbBusFaultIsBfarValid()) {
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PR_EXC("BFAR: 0x%" PRIx32 "\n", _ScbBusFaultAddrGet());
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if (SCB->CFSR & CFSR_BFARVALID_Msk) {
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PR_EXC("BFAR: 0x%" PRIx32 "\n", SCB->BFAR);
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if (escalation) {
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_ScbBusFaultBfarReset();
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/* clear CFSR_BFAR[VALID] to reset */
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SCB->CFSR &= ~CFSR_BFARVALID_Msk;
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}
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}
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/* clear USFR sticky bits */
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_ScbUsageFaultAllFaultsReset();
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SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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@ -130,20 +129,20 @@ static void _MpuFault(const NANO_ESF *esf, int fromHardFault)
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_FaultThreadShow(esf);
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if (_ScbMemFaultIsStacking()) {
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if (SCB->CFSR & CFSR_MSTKERR_Msk) {
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PR_EXC(" Stacking error\n");
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} else if (_ScbMemFaultIsUnstacking()) {
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} else if (SCB->CFSR & CFSR_MUNSTKERR_Msk) {
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PR_EXC(" Unstacking error\n");
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} else if (_ScbMemFaultIsDataAccessViolation()) {
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} else if (SCB->CFSR & CFSR_DACCVIOL_Msk) {
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PR_EXC(" Data Access Violation\n");
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if (_ScbMemFaultIsMmfarValid()) {
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PR_EXC(" Address: 0x%" PRIx32 "\n",
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_ScbMemFaultAddrGet());
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if (SCB->CFSR & CFSR_MMARVALID_Msk) {
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PR_EXC(" Address: 0x%" PRIx32 "\n", SCB->MMFAR);
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if (fromHardFault) {
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_ScbMemFaultMmfarReset();
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/* clear MMAR[VALID] to reset */
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SCB->CFSR &= ~CFSR_MMARVALID_Msk;
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}
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}
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} else if (_ScbMemFaultIsInstrAccessViolation()) {
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} else if (SCB->CFSR & CFSR_IACCVIOL_Msk) {
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PR_EXC(" Instruction Access Violation\n");
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}
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}
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@ -162,26 +161,26 @@ static void _BusFault(const NANO_ESF *esf, int fromHardFault)
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_FaultThreadShow(esf);
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if (_ScbBusFaultIsStacking()) {
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if (SCB->CFSR & CFSR_STKERR_Msk) {
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PR_EXC(" Stacking error\n");
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} else if (_ScbBusFaultIsUnstacking()) {
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} else if (SCB->CFSR & CFSR_UNSTKERR_Msk) {
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PR_EXC(" Unstacking error\n");
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} else if (_ScbBusFaultIsPrecise()) {
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} else if (SCB->CFSR & CFSR_PRECISERR_Msk) {
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PR_EXC(" Precise data bus error\n");
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if (_ScbBusFaultIsBfarValid()) {
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PR_EXC(" Address: 0x%" PRIx32 "\n",
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_ScbBusFaultAddrGet());
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if (SCB->CFSR & CFSR_BFARVALID_Msk) {
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PR_EXC(" Address: 0x%" PRIx32 "\n", SCB->BFAR);
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if (fromHardFault) {
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_ScbBusFaultBfarReset();
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/* clear CFSR_BFAR[VALID] to reset */
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SCB->CFSR &= ~CFSR_BFARVALID_Msk;
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}
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}
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/* it's possible to have both a precise and imprecise fault */
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if (_ScbBusFaultIsImprecise()) {
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if (SCB->CFSR & CFSR_IMPRECISERR_Msk) {
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PR_EXC(" Imprecise data bus error\n");
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}
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} else if (_ScbBusFaultIsImprecise()) {
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} else if (SCB->CFSR & CFSR_IMPRECISERR_Msk) {
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PR_EXC(" Imprecise data bus error\n");
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} else if (_ScbBusFaultIsInstrBusErr()) {
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} else if (SCB->CFSR & CFSR_IBUSERR_Msk) {
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PR_EXC(" Instruction bus error\n");
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}
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}
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@ -201,26 +200,27 @@ static void _UsageFault(const NANO_ESF *esf)
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_FaultThreadShow(esf);
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/* bits are sticky: they stack and must be reset */
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if (_ScbUsageFaultIsDivByZero()) {
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if (SCB->CFSR & CFSR_DIVBYZERO_Msk) {
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PR_EXC(" Division by zero\n");
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}
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if (_ScbUsageFaultIsUnaligned()) {
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if (SCB->CFSR & CFSR_UNALIGNED_Msk) {
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PR_EXC(" Unaligned memory access\n");
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}
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if (_ScbUsageFaultIsNoCp()) {
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if (SCB->CFSR & CFSR_NOCP_Msk) {
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PR_EXC(" No coprocessor instructions\n");
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}
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if (_ScbUsageFaultIsInvalidPcLoad()) {
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if (SCB->CFSR & CFSR_INVPC_Msk) {
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PR_EXC(" Illegal load of EXC_RETURN into PC\n");
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}
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if (_ScbUsageFaultIsInvalidState()) {
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if (SCB->CFSR & CFSR_INVSTATE_Msk) {
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PR_EXC(" Illegal use of the EPSR\n");
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}
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if (_ScbUsageFaultIsUndefinedInstr()) {
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if (SCB->CFSR & CFSR_UNDEFINSTR_Msk) {
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PR_EXC(" Attempt to execute undefined instruction\n");
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}
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_ScbUsageFaultAllFaultsReset();
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/* clear USFR sticky bits */
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SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
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}
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/**
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@ -257,15 +257,15 @@ static void _HardFault(const NANO_ESF *esf)
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#if defined(CONFIG_ARMV6_M)
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_FaultThreadShow(esf);
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#elif defined(CONFIG_ARMV7_M)
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if (_ScbHardFaultIsBusErrOnVectorRead()) {
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if (SCB->HFSR & SCB_HFSR_VECTTBL_Msk) {
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PR_EXC(" Bus fault on vector table read\n");
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} else if (_ScbHardFaultIsForced()) {
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} else if (SCB->HFSR & SCB_HFSR_FORCED_Msk) {
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PR_EXC(" Fault escalation (see below)\n");
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if (_ScbIsMemFault()) {
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if (SCB_MMFSR) {
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_MpuFault(esf, 1);
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} else if (_ScbIsBusFault()) {
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} else if (SCB_BFSR) {
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_BusFault(esf, 1);
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} else if (_ScbIsUsageFault()) {
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} else if (SCB_UFSR) {
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_UsageFault(esf);
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}
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}
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@ -360,7 +360,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
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*/
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void _Fault(const NANO_ESF *esf)
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{
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int fault = _ScbActiveVectorGet();
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int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
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FAULT_DUMP(esf, fault);
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@ -379,7 +379,7 @@ void _FaultInit(void)
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{
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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_ScbDivByZeroFaultEnable();
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SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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@ -88,7 +88,7 @@ _stack_frame_endif:
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eors.n r0, r0
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msr BASEPRI, r0
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/* this reimplements _ScbIsNestedExc() */
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/* this checks to see if we are in a nested exception */
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ldr ip, =_SCS_ICSR
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ldr ip, [ip]
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ands.w ip, #_SCS_ICSR_RETTOBASE
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