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Merge "Merge arm branch into master"

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This commit is contained in:
Anas Nashif 2017-02-11 04:00:58 +00:00
commit 110df98619
58 changed files with 1532 additions and 2977 deletions
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2
arch/arm/core/cortex_m/Makefile
View file

@ -6,6 +6,6 @@ ccflags-y +=-I$(srctree)/include/
asflags-y = $(ccflags-y)
obj-y = vector_table.o reset.o \
nmi_on_reset.o prep_c.o scs.o scb.o nmi.o \
nmi_on_reset.o prep_c.o scb.o nmi.o \
exc_manage.o

22
arch/arm/core/cortex_m/scs.c
View file

@ -1,22 +0,0 @@
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM CORTEX-M Series System Control Space
*
* Most of the SCS interface consists of simple bit-flipping methods, and is
* implemented as inline functions in scs.h. This module thus contains only data
* definitions and more complex routines, if needed.
*/
#include <kernel.h>
#include <arch/cpu.h>
#include <toolchain.h>
#include <sections.h>
/* the linker always puts this object at 0xe000e000 */
volatile struct __scs __scs_section __scs;

88
arch/arm/core/fault.c
View file

@ -64,33 +64,32 @@ void _FaultDump(const NANO_ESF *esf, int fault)
int escalation = 0;
if (3 == fault) { /* hard fault */
escalation = _ScbHardFaultIsForced();
escalation = SCB->HFSR & SCB_HFSR_FORCED_Msk;
PR_EXC("HARD FAULT: %s\n",
escalation ? "Escalation (see below)!"
: "Bus fault on vector table read\n");
}
PR_EXC("MMFSR: 0x%" PRIx32 ", BFSR: 0x%" PRIx32 ", UFSR: 0x%"
PRIx32 "\n",
__scs.scb.cfsr.byte.mmfsr.val,
__scs.scb.cfsr.byte.bfsr.val,
__scs.scb.cfsr.byte.ufsr.val);
PRIx32 "\n", SCB_MMFSR, SCB_BFSR, SCB_MMFSR);
if (_ScbMemFaultIsMmfarValid()) {
PR_EXC("MMFAR: 0x%" PRIx32 "\n", _ScbMemFaultAddrGet());
if (SCB->CFSR & CFSR_MMARVALID_Msk) {
PR_EXC("MMFAR: 0x%" PRIx32 "\n", SCB->MMFAR);
if (escalation) {
_ScbMemFaultMmfarReset();
/* clear MMAR[VALID] to reset */
SCB->CFSR &= ~CFSR_MMARVALID_Msk;
}
}
if (_ScbBusFaultIsBfarValid()) {
PR_EXC("BFAR: 0x%" PRIx32 "\n", _ScbBusFaultAddrGet());
if (SCB->CFSR & CFSR_BFARVALID_Msk) {
PR_EXC("BFAR: 0x%" PRIx32 "\n", SCB->BFAR);
if (escalation) {
_ScbBusFaultBfarReset();
/* clear CFSR_BFAR[VALID] to reset */
SCB->CFSR &= ~CFSR_BFARVALID_Msk;
}
}
/* clear USFR sticky bits */
_ScbUsageFaultAllFaultsReset();
SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
@ -130,20 +129,20 @@ static void _MpuFault(const NANO_ESF *esf, int fromHardFault)
_FaultThreadShow(esf);
if (_ScbMemFaultIsStacking()) {
if (SCB->CFSR & CFSR_MSTKERR_Msk) {
PR_EXC(" Stacking error\n");
} else if (_ScbMemFaultIsUnstacking()) {
} else if (SCB->CFSR & CFSR_MUNSTKERR_Msk) {
PR_EXC(" Unstacking error\n");
} else if (_ScbMemFaultIsDataAccessViolation()) {
} else if (SCB->CFSR & CFSR_DACCVIOL_Msk) {
PR_EXC(" Data Access Violation\n");
if (_ScbMemFaultIsMmfarValid()) {
PR_EXC(" Address: 0x%" PRIx32 "\n",
_ScbMemFaultAddrGet());
if (SCB->CFSR & CFSR_MMARVALID_Msk) {
PR_EXC(" Address: 0x%" PRIx32 "\n", SCB->MMFAR);
if (fromHardFault) {
_ScbMemFaultMmfarReset();
/* clear MMAR[VALID] to reset */
SCB->CFSR &= ~CFSR_MMARVALID_Msk;
}
}
} else if (_ScbMemFaultIsInstrAccessViolation()) {
} else if (SCB->CFSR & CFSR_IACCVIOL_Msk) {
PR_EXC(" Instruction Access Violation\n");
}
}
@ -162,26 +161,26 @@ static void _BusFault(const NANO_ESF *esf, int fromHardFault)
_FaultThreadShow(esf);
if (_ScbBusFaultIsStacking()) {
if (SCB->CFSR & CFSR_STKERR_Msk) {
PR_EXC(" Stacking error\n");
} else if (_ScbBusFaultIsUnstacking()) {
} else if (SCB->CFSR & CFSR_UNSTKERR_Msk) {
PR_EXC(" Unstacking error\n");
} else if (_ScbBusFaultIsPrecise()) {
} else if (SCB->CFSR & CFSR_PRECISERR_Msk) {
PR_EXC(" Precise data bus error\n");
if (_ScbBusFaultIsBfarValid()) {
PR_EXC(" Address: 0x%" PRIx32 "\n",
_ScbBusFaultAddrGet());
if (SCB->CFSR & CFSR_BFARVALID_Msk) {
PR_EXC(" Address: 0x%" PRIx32 "\n", SCB->BFAR);
if (fromHardFault) {
_ScbBusFaultBfarReset();
/* clear CFSR_BFAR[VALID] to reset */
SCB->CFSR &= ~CFSR_BFARVALID_Msk;
}
}
/* it's possible to have both a precise and imprecise fault */
if (_ScbBusFaultIsImprecise()) {
if (SCB->CFSR & CFSR_IMPRECISERR_Msk) {
PR_EXC(" Imprecise data bus error\n");
}
} else if (_ScbBusFaultIsImprecise()) {
} else if (SCB->CFSR & CFSR_IMPRECISERR_Msk) {
PR_EXC(" Imprecise data bus error\n");
} else if (_ScbBusFaultIsInstrBusErr()) {
} else if (SCB->CFSR & CFSR_IBUSERR_Msk) {
PR_EXC(" Instruction bus error\n");
}
}
@ -201,26 +200,27 @@ static void _UsageFault(const NANO_ESF *esf)
_FaultThreadShow(esf);
/* bits are sticky: they stack and must be reset */
if (_ScbUsageFaultIsDivByZero()) {
if (SCB->CFSR & CFSR_DIVBYZERO_Msk) {
PR_EXC(" Division by zero\n");
}
if (_ScbUsageFaultIsUnaligned()) {
if (SCB->CFSR & CFSR_UNALIGNED_Msk) {
PR_EXC(" Unaligned memory access\n");
}
if (_ScbUsageFaultIsNoCp()) {
if (SCB->CFSR & CFSR_NOCP_Msk) {
PR_EXC(" No coprocessor instructions\n");
}
if (_ScbUsageFaultIsInvalidPcLoad()) {
if (SCB->CFSR & CFSR_INVPC_Msk) {
PR_EXC(" Illegal load of EXC_RETURN into PC\n");
}
if (_ScbUsageFaultIsInvalidState()) {
if (SCB->CFSR & CFSR_INVSTATE_Msk) {
PR_EXC(" Illegal use of the EPSR\n");
}
if (_ScbUsageFaultIsUndefinedInstr()) {
if (SCB->CFSR & CFSR_UNDEFINSTR_Msk) {
PR_EXC(" Attempt to execute undefined instruction\n");
}
_ScbUsageFaultAllFaultsReset();
/* clear USFR sticky bits */
SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
}
/**
@ -257,15 +257,15 @@ static void _HardFault(const NANO_ESF *esf)
#if defined(CONFIG_ARMV6_M)
_FaultThreadShow(esf);
#elif defined(CONFIG_ARMV7_M)
if (_ScbHardFaultIsBusErrOnVectorRead()) {
if (SCB->HFSR & SCB_HFSR_VECTTBL_Msk) {
PR_EXC(" Bus fault on vector table read\n");
} else if (_ScbHardFaultIsForced()) {
} else if (SCB->HFSR & SCB_HFSR_FORCED_Msk) {
PR_EXC(" Fault escalation (see below)\n");
if (_ScbIsMemFault()) {
if (SCB_MMFSR) {
_MpuFault(esf, 1);
} else if (_ScbIsBusFault()) {
} else if (SCB_BFSR) {
_BusFault(esf, 1);
} else if (_ScbIsUsageFault()) {
} else if (SCB_UFSR) {
_UsageFault(esf);
}
}
@ -360,7 +360,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
*/
void _Fault(const NANO_ESF *esf)
{
int fault = _ScbActiveVectorGet();
int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
FAULT_DUMP(esf, fault);
@ -379,7 +379,7 @@ void _FaultInit(void)
{
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
_ScbDivByZeroFaultEnable();
SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */

2
arch/arm/core/fault_s.S
View file

@ -88,7 +88,7 @@ _stack_frame_endif:
eors.n r0, r0
msr BASEPRI, r0
/* this reimplements _ScbIsNestedExc() */
/* this checks to see if we are in a nested exception */
ldr ip, =_SCS_ICSR
ldr ip, [ip]
ands.w ip, #_SCS_ICSR_RETTOBASE

18
arch/arm/include/cortex_m/exc.h
View file

@ -53,7 +53,8 @@ static ALWAYS_INLINE int _IsInIsr(void)
#if defined(CONFIG_ARMV6_M)
return (vector > 10) || (vector == 3);
#elif defined(CONFIG_ARMV7_M)
return (vector > 10) || (vector && _ScbIsNestedExc());
return (vector > 10) ||
(vector && !(SCB->ICSR & SCB_ICSR_RETTOBASE_Msk));
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
@ -84,9 +85,9 @@ static ALWAYS_INLINE void _ExcSetup(void)
NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO);
NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO);
_ScbUsageFaultEnable();
_ScbBusFaultEnable();
_ScbMemFaultEnable();
/* Enable Usage, Mem, & Bus Faults */
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
SCB_SHCSR_BUSFAULTENA_Msk;
#endif
}
@ -102,11 +103,12 @@ static ALWAYS_INLINE void _ClearFaults(void)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/* Reset all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
SCB_CFSR_MEMFAULTSR_Msk |
SCB_CFSR_BUSFAULTSR_Msk;
_ScbHardFaultAllFaultsReset();
/* Clear all Hard Faults - HFSR is write-one-to-clear */
SCB->HFSR = 0xffffffff;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */

89
arch/arm/soc/st_stm32/stm32f3/rcc_registers.h
View file

@ -1,89 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F3X_CLOCK_H_
#define _STM32F3X_CLOCK_H_
/**
* @brief Driver for Reset & Clock Control of STM32F3x family processor.
*
* Based on reference manual:
* STM32F303xB.C.D.E advanced ARM ® -based 32-bit MCU
* STM32F334xx advanced ARM ® -based 32-bit MCU
* STM32F37xx advanced ARM ® -based 32-bit MCU
*
* Chapter 8: Reset and clock control (RCC)
*/
/**
* @brief Reset and Clock Control
*/
union __rcc_cr {
uint32_t val;
struct {
uint32_t hsion :1 __packed;
uint32_t hsirdy :1 __packed;
uint32_t rsvd__2 :1 __packed;
uint32_t hsitrim :5 __packed;
uint32_t hsical :8 __packed;
uint32_t hseon :1 __packed;
uint32_t hserdy :1 __packed;
uint32_t hsebyp :1 __packed;
uint32_t csson :1 __packed;
uint32_t rsvd__20_23 :4 __packed;
uint32_t pllon :1 __packed;
uint32_t pllrdy :1 __packed;
uint32_t rsvd__26_31 :6 __packed;
} bit;
};
union __rcc_cfgr {
uint32_t val;
struct {
uint32_t sw :2 __packed;
uint32_t sws :2 __packed;
uint32_t hpre :4 __packed;
uint32_t ppre1 :3 __packed;
uint32_t ppre2 :3 __packed;
uint32_t rsvd__14_15 :2 __packed;
uint32_t pllsrc :1 __packed;
uint32_t pllxtpre :1 __packed;
uint32_t pllmul :4 __packed;
uint32_t rsvd__22_23 :2 __packed;
uint32_t mco :3 __packed;
uint32_t rsvd__27 :1 __packed;
uint32_t mcopre :3 __packed;
uint32_t pllnodiv :1 __packed;
} bit;
};
union __rcc_cfgr2 {
uint32_t val;
struct {
uint32_t prediv :4 __packed;
uint32_t adc12pres : 5 __packed;
uint32_t rsvd__9_31 :23 __packed;
} bit;
};
struct stm32f3x_rcc {
union __rcc_cr cr;
union __rcc_cfgr cfgr;
uint32_t cir;
uint32_t apb2rstr;
uint32_t apb1rstr;
uint32_t ahbenr;
uint32_t apb2enr;
uint32_t apb1enr;
uint32_t bdcr;
uint32_t csr;
uint32_t ahbrstr;
union __rcc_cfgr2 cfgr2;
uint32_t cfgr3;
};
#endif /* _STM32F3X_CLOCK_H_ */

3
arch/arm/soc/st_stm32/stm32f3/soc.c
View file

@ -42,7 +42,8 @@ static int stm32f3_init(struct device *arg)
irq_unlock(key);
/* Update CMSIS SystemCoreClock variable (HCLK) */
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
/* At reset, System core clock is set to 4MHz */
SystemCoreClock = 4000000;
return 0;
}

7
arch/arm/soc/st_stm32/stm32f3/soc.h
View file

@ -52,6 +52,13 @@ enum stm32f3x_pin_config_mode {
#include <stm32f3xx_ll_usart.h>
#endif
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#include <stm32f3xx_ll_utils.h>
#include <stm32f3xx_ll_bus.h>
#include <stm32f3xx_ll_rcc.h>
#include <stm32f3xx_ll_system.h>
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F3_SOC_H_ */

22
arch/arm/soc/st_stm32/stm32f3/soc_config.c
View file

@ -29,25 +29,3 @@ int stm32_get_pin_config(int pin, int func)
/* encode and return the 'real' alternate function number */
return STM32_PINFUNC(func, STM32F3X_PIN_CONFIG_AF);
}
clock_control_subsys_t stm32_get_port_clock(int port)
{
const clock_control_subsys_t ports_to_clock[STM32_PORTS_MAX] = {
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPA),
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPB),
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPC),
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPD),
#ifdef CONFIG_SOC_STM32F334X8
UINT_TO_POINTER(0),
#else
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPE),
#endif
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPF),
};
if (port > STM32_PORTF) {
return NULL;
}
return ports_to_clock[port];
}

9
arch/arm/soc/st_stm32/stm32f3/soc_gpio.c
View file

@ -117,7 +117,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
if (crpin > 7) {
afr = &gpio->afrh;
crpin -= 7;
crpin -= 8;
}
/* clear AF bits */
@ -188,7 +188,12 @@ int stm32_gpio_enable_int(int port, int pin)
struct device *clk =
device_get_binding(STM32_CLOCK_CONTROL_NAME);
clock_control_on(clk, UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_SYSCFG));
struct stm32_pclken pclken = {
.bus = STM32_CLOCK_BUS_APB2,
.enr = LL_APB2_GRP1_PERIPH_SYSCFG
};
clock_control_on(clk, (clock_control_subsys_t *) &pclken);
int shift = 0;

1
arch/arm/soc/st_stm32/stm32f3/soc_registers.h
View file

@ -8,7 +8,6 @@
#define _STM32F3X_SOC_REGISTERS_H_
/* include register mapping headers */
#include "rcc_registers.h"
#include "flash_registers.h"
#include "gpio_registers.h"

176
arch/arm/soc/st_stm32/stm32l4/rcc_registers.h
View file

@ -1,176 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32L4X_CLOCK_H_
#define _STM32L4X_CLOCK_H_
/**
* @brief Driver for Reset & Clock Control of STM32L4x6 family processor.
*/
enum {
STM32L4X_RCC_CFG_PLL_SRC_MSI = 0x1,
STM32L4X_RCC_CFG_PLL_SRC_HSI = 0x2,
STM32L4X_RCC_CFG_PLL_SRC_HSE = 0x3,
};
enum {
STM32L4X_RCC_CFG_PLL_Q_R_0 = 0x1,
STM32L4X_RCC_CFG_PLL_Q_R_2 = 0x2,
};
enum {
STM32L4X_RCC_CFG_SYSCLK_SRC_MSI = 0x0,
STM32L4X_RCC_CFG_SYSCLK_SRC_HSI = 0x1,
STM32L4X_RCC_CFG_SYSCLK_SRC_HSE = 0x2,
STM32L4X_RCC_CFG_SYSCLK_SRC_PLL = 0x3,
};
enum {
STM32L4X_RCC_CFG_HCLK_DIV_0 = 0x0,
STM32L4X_RCC_CFG_HCLK_DIV_2 = 0x4,
STM32L4X_RCC_CFG_HCLK_DIV_4 = 0x5,
STM32L4X_RCC_CFG_HCLK_DIV_8 = 0x6,
STM32L4X_RCC_CFG_HCLK_DIV_16 = 0x7,
};
enum {
STM32L4X_RCC_CFG_SYSCLK_DIV_0 = 0x0,
STM32L4X_RCC_CFG_SYSCLK_DIV_2 = 0x8,
STM32L4X_RCC_CFG_SYSCLK_DIV_4 = 0x9,
STM32L4X_RCC_CFG_SYSCLK_DIV_8 = 0xa,
STM32L4X_RCC_CFG_SYSCLK_DIV_16 = 0xb,
STM32L4X_RCC_CFG_SYSCLK_DIV_64 = 0xc,
STM32L4X_RCC_CFG_SYSCLK_DIV_128 = 0xd,
STM32L4X_RCC_CFG_SYSCLK_DIV_256 = 0xe,
STM32L4X_RCC_CFG_SYSCLK_DIV_512 = 0xf,
};
enum {
STM32L4X_RCC_CFG_MCO_DIV_0 = 0x0,
STM32L4X_RCC_CFG_MCO_DIV_2 = 0x1,
STM32L4X_RCC_CFG_MCO_DIV_4 = 0x2,
STM32L4X_RCC_CFG_MCO_DIV_8 = 0x3,
STM32L4X_RCC_CFG_MCO_DIV_16 = 0x4,
};
/**
* @brief Reset and Clock Control
*/
union __rcc_cr {
uint32_t val;
struct {
uint32_t msion :1 __packed;
uint32_t msirdy :1 __packed;
uint32_t msipllen :1 __packed;
uint32_t msirgsel :1 __packed;
uint32_t msirange :4 __packed;
uint32_t hsion :1 __packed;
uint32_t hsikeron :1 __packed;
uint32_t hsirdy :1 __packed;
uint32_t hsiasfs :1 __packed;
uint32_t rsvd__12_15 :4 __packed;
uint32_t hseon :1 __packed;
uint32_t hserdy :1 __packed;
uint32_t hsebyp :1 __packed;
uint32_t csson :1 __packed;
uint32_t rsvd__20_23 :4 __packed;
uint32_t pllon :1 __packed;
uint32_t pllrdy :1 __packed;
uint32_t pllsai1on :1 __packed;
uint32_t pllsai1rdy :1 __packed;
/*
* SAI2 not present on L4x2, L431xx, STM32L433xx,
* and STM32L443xx.
*/
uint32_t pllsai2on :1 __packed;
uint32_t pllsai2rdy :1 __packed;
uint32_t rsvd__30_31 :2 __packed;
} bit;
};
union __rcc_cfgr {
uint32_t val;
struct {
uint32_t sw :2 __packed;
uint32_t sws :2 __packed;
uint32_t hpre :4 __packed;
uint32_t ppre1 :3 __packed;
uint32_t ppre2 :3 __packed;
uint32_t stopwuck :1 __packed;
uint32_t rsvd__16_23 :8 __packed;
uint32_t mcosel :3 __packed; /* 2 bits long on L4x{1,5,6} */
uint32_t mcopre :3 __packed;
uint32_t rsvd__31 :1 __packed;
} bit;
};
union __rcc_pllcfgr {
uint32_t val;
struct {
uint32_t pllsrc :2 __packed;
uint32_t rsvd__2_3 :2 __packed;
uint32_t pllm :3 __packed;
uint32_t rsvd__7 :1 __packed;
uint32_t plln :7 __packed;
uint32_t rsvd__15 :1 __packed;
uint32_t pllpen :1 __packed;
uint32_t pllp :1 __packed;
uint32_t rsvd__18_19 :2 __packed;
uint32_t pllqen :1 __packed;
uint32_t pllq :2 __packed;
uint32_t rsvd__23 :1 __packed;
uint32_t pllren :1 __packed;
uint32_t pllr :2 __packed;
uint32_t pllpdiv :5 __packed; /* Not present on L4x{1,5,6} */
} bit;
};
struct stm32l4x_rcc {
union __rcc_cr cr;
uint32_t icscr;
union __rcc_cfgr cfgr;
union __rcc_pllcfgr pllcfgr;
uint32_t pllsai1cfgr;
uint32_t pllsai2cfgr;
uint32_t cier;
uint32_t cifr;
uint32_t cicr;
uint32_t rsvd_0;
uint32_t ahb1rstr;
uint32_t ahb2rstr;
uint32_t ahb3rstr;
uint32_t rsvd_1;
uint32_t apb1rstr1;
uint32_t apb1rstr2;
uint32_t apb2rstr;
uint32_t rsvd_2;
uint32_t ahb1enr;
uint32_t ahb2enr;
uint32_t ahb3enr;
uint32_t rsvd_3;
uint32_t apb1enr1;
uint32_t apb1enr2;
uint32_t apb2enr;
uint32_t rsvd_4;
uint32_t ahb1smenr;
uint32_t ahb2smenr;
uint32_t ahb3smenr;
uint32_t rsvd_5;
uint32_t apb1smenr1;
uint32_t apb1smenr2;
uint32_t apb2smenr;
uint32_t rsvd_6;
uint32_t ccipr;
uint32_t rsvd_7;
uint32_t bdcr;
uint32_t csr;
};
#endif /* _STM32L4X_CLOCK_H_ */

3
arch/arm/soc/st_stm32/stm32l4/soc.c
View file

@ -43,7 +43,8 @@ static int stm32l4_init(struct device *arg)
irq_unlock(key);
/* Update CMSIS SystemCoreClock variable (HCLK) */
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
/* At reset, System core clock is set to 4MHz */
SystemCoreClock = 4000000;
return 0;
}

7
arch/arm/soc/st_stm32/stm32l4/soc.h
View file

@ -35,6 +35,13 @@
#include <stm32l4xx_ll_usart.h>
#endif
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#include <stm32l4xx_ll_utils.h>
#include <stm32l4xx_ll_bus.h>
#include <stm32l4xx_ll_rcc.h>
#include <stm32l4xx_ll_system.h>
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#endif /* !_ASMLANGUAGE */
#endif /* _STM32L4X_SOC_H_ */

8
arch/arm/soc/st_stm32/stm32l4/soc_gpio.c
View file

@ -214,8 +214,12 @@ int stm32_gpio_enable_int(int port, int pin)
struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
uint32_t *reg;
clock_control_on(clk, (clock_control_subsys_t *)
STM32L4X_CLOCK_SUBSYS_SYSCFG);
/* Enable SYSCFG clock */
struct stm32_pclken pclken = {
.bus = STM32_CLOCK_BUS_APB2,
.enr = LL_APB2_GRP1_PERIPH_SYSCFG
};
clock_control_on(clk, (clock_control_subsys_t *) &pclken);
if (pin <= STM32L4X_PIN3) {
reg = &syscfg->exticr1;

20
arch/arm/soc/st_stm32/stm32l4/soc_pinmux.c
View file

@ -99,23 +99,3 @@ int stm32_get_pin_config(int pin, int func)
}
return -EINVAL;
}
clock_control_subsys_t stm32_get_port_clock(int port)
{
const clock_control_subsys_t ports_to_clock[STM32_PORTS_MAX] = {
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOA),
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOB),
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOC),
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOD),
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOE),
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOF),
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOG),
UINT_TO_POINTER(STM32L4X_CLOCK_SUBSYS_GPIOH),
};
if (port > STM32_PORTH) {
return NULL;
}
return ports_to_clock[port];
}

1
arch/arm/soc/st_stm32/stm32l4/soc_registers.h
View file

@ -9,7 +9,6 @@
#define _STM32L4X_SOC_REGISTERS_H_
/* include register mapping headers */
#include "rcc_registers.h"
#include "flash_registers.h"
#include "syscfg_registers.h"