michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: riscv: pmp: Fix RV64 compatibility of register size

Browse source 
In RV64, all general-purpose registers and pmpcfg CSR are 64-bit
instead of 32-bit. Fix these registers and related C variables/literals
to be 32/64-bit compatible.

Signed-off-by: Jim Shu <cwshu09@gmail.com>
This commit is contained in:
Jim Shu 2022-01-15 18:42:44 +08:00 • committed by Anas Nashif
commit 10e618ff33
2 changed files with 34 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

10
arch/riscv/core/pmp/core_pmp.c
View file

@ -294,11 +294,11 @@ static int riscv_pmp_set(unsigned int index, uint8_t cfg_val, ulong_t addr_val)
pmpcfg_csr = CSR_PMPCFG0 + PMPCFG_NUM(index);
pmpaddr_csr = CSR_PMPADDR0 + index;
shift = PMPCFG_SHIFT(index);
mask = 0xFF << shift;
mask = 0xFFUL << shift;
reg_val = csr_read_enum(pmpcfg_csr);
reg_val = reg_val & ~mask;
reg_val = reg_val | (cfg_val << shift);
reg_val = reg_val | ((ulong_t)cfg_val << shift);
csr_write_enum(pmpaddr_csr, addr_val);
csr_write_enum(pmpcfg_csr, reg_val);
@ -321,7 +321,7 @@ static int riscv_pmp_get(unsigned int index, uint8_t *cfg_val, ulong_t *addr_val
pmpcfg_csr = CSR_PMPCFG0 + PMPCFG_NUM(index);
pmpaddr_csr = CSR_PMPADDR0 + index;
shift = PMPCFG_SHIFT(index);
mask = 0xFF << shift;
mask = 0xFFUL << shift;
reg_val = csr_read_enum(pmpcfg_csr);
*cfg_val = (reg_val & mask) >> shift;
@ -353,11 +353,11 @@ void riscv_pmpcfg_set_range(uint8_t min_index, uint8_t max_index, uint8_t *u8_pm
for (int index = min_index; index <= max_index; index++) {
shift = PMPCFG_SHIFT(index);
cfg_mask |= (0xFF << shift);
cfg_mask |= (0xFFUL << shift);
/* If u8_pmpcfg is NULL, new_pmpcfg is always 0 to clear pmpcfg CSR. */
if (u8_pmpcfg != NULL) {
new_pmpcfg |= (u8_pmpcfg[index] << shift);
new_pmpcfg |= ((ulong_t) u8_pmpcfg[index]) << shift;
}
/* If index+1 is new CSR or it's last index, apply new_pmpcfg value to the CSR. */

58
include/arch/riscv/syscall.h
View file

@ -42,13 +42,13 @@ static inline uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg5, uintptr_t arg6,
uintptr_t call_id)
{
register uint32_t a0 __asm__ ("a0") = arg1;
register uint32_t a1 __asm__ ("a1") = arg2;
register uint32_t a2 __asm__ ("a2") = arg3;
register uint32_t a3 __asm__ ("a3") = arg4;
register uint32_t a4 __asm__ ("a4") = arg5;
register uint32_t a5 __asm__ ("a5") = arg6;
register uint32_t a7 __asm__ ("a7") = call_id;
register ulong_t a0 __asm__ ("a0") = arg1;
register ulong_t a1 __asm__ ("a1") = arg2;
register ulong_t a2 __asm__ ("a2") = arg3;
register ulong_t a3 __asm__ ("a3") = arg4;
register ulong_t a4 __asm__ ("a4") = arg5;
register ulong_t a5 __asm__ ("a5") = arg6;
register ulong_t a7 __asm__ ("a7") = call_id;
__asm__ volatile ("ecall"
: "+r" (a0)
@ -63,12 +63,12 @@ static inline uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg5,
uintptr_t call_id)
{
register uint32_t a0 __asm__ ("a0") = arg1;
register uint32_t a1 __asm__ ("a1") = arg2;
register uint32_t a2 __asm__ ("a2") = arg3;
register uint32_t a3 __asm__ ("a3") = arg4;
register uint32_t a4 __asm__ ("a4") = arg5;
register uint32_t a7 __asm__ ("a7") = call_id;
register ulong_t a0 __asm__ ("a0") = arg1;
register ulong_t a1 __asm__ ("a1") = arg2;
register ulong_t a2 __asm__ ("a2") = arg3;
register ulong_t a3 __asm__ ("a3") = arg4;
register ulong_t a4 __asm__ ("a4") = arg5;
register ulong_t a7 __asm__ ("a7") = call_id;
__asm__ volatile ("ecall"
: "+r" (a0)
@ -81,11 +81,11 @@ static inline uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t call_id)
{
register uint32_t a0 __asm__ ("a0") = arg1;
register uint32_t a1 __asm__ ("a1") = arg2;
register uint32_t a2 __asm__ ("a2") = arg3;
register uint32_t a3 __asm__ ("a3") = arg4;
register uint32_t a7 __asm__ ("a7") = call_id;
register ulong_t a0 __asm__ ("a0") = arg1;
register ulong_t a1 __asm__ ("a1") = arg2;
register ulong_t a2 __asm__ ("a2") = arg3;
register ulong_t a3 __asm__ ("a3") = arg4;
register ulong_t a7 __asm__ ("a7") = call_id;
__asm__ volatile ("ecall"
: "+r" (a0)
@ -98,10 +98,10 @@ static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3,
uintptr_t call_id)
{
register uint32_t a0 __asm__ ("a0") = arg1;
register uint32_t a1 __asm__ ("a1") = arg2;
register uint32_t a2 __asm__ ("a2") = arg3;
register uint32_t a7 __asm__ ("a7") = call_id;
register ulong_t a0 __asm__ ("a0") = arg1;
register ulong_t a1 __asm__ ("a1") = arg2;
register ulong_t a2 __asm__ ("a2") = arg3;
register ulong_t a7 __asm__ ("a7") = call_id;
__asm__ volatile ("ecall"
: "+r" (a0)
@ -113,9 +113,9 @@ static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
uintptr_t call_id)
{
register uint32_t a0 __asm__ ("a0") = arg1;
register uint32_t a1 __asm__ ("a1") = arg2;
register uint32_t a7 __asm__ ("a7") = call_id;
register ulong_t a0 __asm__ ("a0") = arg1;
register ulong_t a1 __asm__ ("a1") = arg2;
register ulong_t a7 __asm__ ("a7") = call_id;
__asm__ volatile ("ecall"
: "+r" (a0)
@ -126,8 +126,8 @@ static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id)
{
register uint32_t a0 __asm__ ("a0") = arg1;
register uint32_t a7 __asm__ ("a7") = call_id;
register ulong_t a0 __asm__ ("a0") = arg1;
register ulong_t a7 __asm__ ("a7") = call_id;
__asm__ volatile ("ecall"
: "+r" (a0)
@ -138,8 +138,8 @@ static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id)
{
register uint32_t a0 __asm__ ("a0");
register uint32_t a7 __asm__ ("a7") = call_id;
register ulong_t a0 __asm__ ("a0");
register ulong_t a7 __asm__ ("a7") = call_id;
__asm__ volatile ("ecall"
: "+r" (a0)