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Use SoC instead of platform.

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Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.

Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2015-12-17 08:54:35 -05:00
commit 10bb38c186
175 changed files with 220 additions and 232 deletions
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156
arch/arm/soc/fsl_frdm_k64f/Kconfig Normal file
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# Kconfig - FSL FRDM K64F platform configuration options
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_FSL_FRDM_K64F
config SOC
default fsl_frdm_k64f
config NUM_IRQ_PRIO_BITS
int
default 4
config NUM_IRQS
int
# must be >= the highest interrupt number used
default 86
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 25000000
config WDOG_INIT
def_bool y
# omit prompt to signify a "hidden" option
help
This processor enables the watchdog timer with a short timeout
upon reset. Therefore, this requires that the watchdog be configured
during reset handling.
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
if UART_K20
config UART_K20_PORT_0
def_bool y
if UART_K20_PORT_0
config UART_K20_PORT_0_BASE_ADDR
default 0x4006A000
config UART_K20_PORT_0_IRQ
default 31
config UART_K20_PORT_0_IRQ_PRI
default 3
config UART_K20_PORT_0_BAUD_RATE
default 115200
config UART_K20_PORT_0_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_1
def_bool y
if UART_K20_PORT_1
config UART_K20_PORT_1_BASE_ADDR
default 0x4006B000
config UART_K20_PORT_1_IRQ
default 33
config UART_K20_PORT_1_IRQ_PRI
default 3
config UART_K20_PORT_1_BAUD_RATE
default 115200
config UART_K20_PORT_1_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_2
def_bool y
if UART_K20_PORT_2
config UART_K20_PORT_2_BASE_ADDR
default 0x4006C000
config UART_K20_PORT_2_IRQ
default 35
config UART_K20_PORT_2_IRQ_PRI
default 3
config UART_K20_PORT_2_BAUD_RATE
default 115200
config UART_K20_PORT_2_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_3
def_bool y
if UART_K20_PORT_3
config UART_K20_PORT_3_BASE_ADDR
default 0x4006D000
config UART_K20_PORT_3_IRQ
default 37
config UART_K20_PORT_3_IRQ_PRI
default 3
config UART_K20_PORT_3_BAUD_RATE
default 115200
config UART_K20_PORT_3_CLK_FREQ
default 120000000
endif
config UART_K20_PORT_4
def_bool y
if UART_K20_PORT_4
config UART_K20_PORT_4_BASE_ADDR
default 0x400EA000
config UART_K20_PORT_4_IRQ
default 66
config UART_K20_PORT_4_IRQ_PRI
default 3
config UART_K20_PORT_4_BAUD_RATE
default 115200
config UART_K20_PORT_4_CLK_FREQ
default 120000000
endif
endif # UART_K20
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
config UART_CONSOLE_IRQ
default 31
config UART_CONSOLE_IRQ_PRI
default 3
endif
if BLUETOOTH_UART
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1"
config BLUETOOTH_UART_IRQ
default 33
config BLUETOOTH_UART_IRQ_PRI
default 3
endif
endif

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arch/arm/soc/fsl_frdm_k64f/Kconfig.soc Normal file
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config SOC_FSL_FRDM_K64F
bool "Freescale FRDM-K64F"
select CPU_CORTEX_M
select CPU_CORTEX_M4

6
arch/arm/soc/fsl_frdm_k64f/Makefile Normal file
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obj-y += soc_config.o
obj-y += soc.o
obj-y += nmi_on_reset.o
obj-y += wdog.o
obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o

10
arch/arm/soc/fsl_frdm_k64f/README.txt Normal file
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Notes on the FSL FRDM K64F SRAM base address and size
Although the K64F CPU has 64 kB of SRAM at 0x1FFF0000 (code space), it is not
used by the FSL FRDM K64F platform. Only the 192 kB region based at the
standard ARMv7-M SRAM base address of 0x20000000 is supported.
As such the following values are used:
CONFIG_SRAM_BASE_ADDRESS=0x20000000
CONFIG_SRAM_SIZE=64 # Measured in kB

84
arch/arm/soc/fsl_frdm_k64f/irq_vector_table.c Normal file
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/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief IRQ part of vector table
*
* This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases:
*
* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
* binds _isr_wrapper() to all the IRQ entries in the vector table.
*
* b) When the platform is written so that device ISRs are installed directly in
* the vector table, they are enumerated here.
*/
#include <toolchain.h>
#include <sections.h>
#if defined(CONFIG_CONSOLE_HANDLER)
#include <soc.h>
#include <console/uart_console.h>
#endif /* CONFIG_CONSOLE_HANDLER */
#if defined(CONFIG_BLUETOOTH_UART)
#include <soc.h>
#include <bluetooth/uart.h>
#endif /* CONFIG_BLUETOOTH_UART */
extern void _isr_wrapper(void);
typedef void (*vth)(void); /* Vector Table Handler */
#if defined(CONFIG_SW_ISR_TABLE)
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _isr_wrapper,
};
#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
extern void _irq_spurious(void);
#if defined(CONFIG_CONSOLE_HANDLER)
static void _uart_console_isr(void)
{
uart_console_isr(NULL);
_IntExit();
}
#endif /* CONFIG_CONSOLE_HANDLER */
#if defined(CONFIG_BLUETOOTH_UART)
static void _bt_uart_isr(void)
{
bt_uart_isr(NULL);
_IntExit();
}
#endif /* CONFIG_BLUETOOTH_UART */
/* placeholders: fill with real ISRs */
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
#if defined(CONFIG_CONSOLE_HANDLER)
[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
#endif
#if defined(CONFIG_BLUETOOTH_UART)
[CONFIG_BLUETOOTH_UART_IRQ] = _bt_uart_isr,
#endif
};
#endif /* CONFIG_SW_ISR_TABLE */

32
arch/arm/soc/fsl_frdm_k64f/linker.cmd Normal file
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/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/
/*
* K64F Flash configuration fields
* These are 16 bytes, which must be loaded to address 0x400, and include
* default protection and security settings.
* They are loaded at reset to various Flash Memory module (FTFE) registers.
*/
#define SKIP_TO_SECURITY_FRDM_K64F . = 0x400;
#include <arch/arm/cortex_m/scripts/linker.cmd>

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arch/arm/soc/fsl_frdm_k64f/nmi_on_reset.S Normal file
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/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Default basic NMI handler before the kernel is up
*
* Provide a default handler for NMI before the system is up. The default action
* is to hard hang, sleeping.
*
* This might be preferable than rebooting to help debugging, or because
* rebooting might trigger the exact same problem over and over.
*/
#define _ASMLANGUAGE
#include <toolchain.h>
#include <sections.h>
_ASM_FILE_PROLOGUE
GTEXT(_SysNmiOnReset)
SECTION_FUNC(TEXT, _SysNmiOnReset)
wfi
b _SysNmiOnReset

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arch/arm/soc/fsl_frdm_k64f/soc.c Normal file
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/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief System/hardware module for fsl_frdm_k64f platform
*
* This module provides routines to initialize and support board-level
* hardware for the fsl_frdm_k64f platform.
*/
#include <nanokernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <drivers/k20_mcg.h>
#include <uart.h>
#include <drivers/k20_pcr.h>
#include <drivers/k20_sim.h>
#include <drivers/k6x_mpu.h>
#include <drivers/k6x_pmc.h>
#include <sections.h>
/* board's setting for PLL multipler (PRDIV0) */
#define FRDM_K64F_PLL_DIV_20 (20 - 1)
/* board's setting for PLL multipler (VDIV0) */
#define FRDM_K64F_PLL_MULT_48 (48 - 24)
#ifdef CONFIG_RUNTIME_NMI
extern void _NmiInit(void);
#define NMI_INIT() _NmiInit()
#else
#define NMI_INIT()
#endif
/*
* K64F Flash configuration fields
* These 16 bytes, which must be loaded to address 0x400, include default
* protection and security settings.
* They are loaded at reset to various Flash Memory module (FTFE) registers.
*
* The structure is:
* -Backdoor Comparison Key for unsecuring the MCU - 8 bytes
* -Program flash protection bytes, 4 bytes, written to FPROT0-3
* -Flash security byte, 1 byte, written to FSEC
* -Flash nonvolatile option byte, 1 byte, written to FOPT
* -Reserved, 1 byte, (Data flash protection byte for FlexNVM)
* -Reserved, 1 byte, (EEPROM protection byte for FlexNVM)
*
*/
uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
/* Backdoor Comparison Key (unused) */
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
*/
0xFF, 0xFF, 0xFF, 0xFF,
/*
* Flash security: Backdoor key disabled, Mass erase enabled,
* Factory access enabled, MCU is unsecure
*/
0xFE,
/* Flash nonvolatile option: NMI enabled, EzPort enabled, Normal boot */
0xFF,
/* Reserved for FlexNVM feature (unsupported by this MCU) */
0xFF, 0xFF};
/**
*
* @brief Initialize the system clock
*
* This routine will configure the multipurpose clock generator (MCG) to
* set up the system clock.
* The MCG has nine possible modes, including Stop mode. This routine assumes
* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
* It transitions through the FLL Bypassed External (FBE) and
* PLL Bypassed External (PBE) modes to get to the desired
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
* clock.
*
* @return N/A
*
*/
static void clkInit(void)
{
uint8_t temp_reg;
K20_MCG_t *mcg_p = (K20_MCG_t *)PERIPH_ADDR_BASE_MCG; /* clk gen. ctl */
/*
* Select the 50 Mhz external clock as the MCG OSC clock.
* MCG Control 7 register:
* - Select OSCCLK0 / XTAL
*/
temp_reg = mcg_p->c7 & ~MCG_C7_OSCSEL_MASK;
temp_reg |= MCG_C7_OSCSEL_OSC0;
mcg_p->c7 = temp_reg;
/*
* Transition MCG from FEI mode (at reset) to FBE mode.
*/
/*
* MCG Control 2 register:
* - Set oscillator frequency range = very high for 50 MHz external
* clock
* - Set oscillator mode = low power
* - Select external reference clock as the oscillator source
*/
temp_reg = mcg_p->c2 &
~(MCG_C2_RANGE_MASK | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK);
temp_reg |=
(MCG_C2_RANGE_VHIGH | MCG_C2_HGO_LO_PWR | MCG_C2_EREFS_EXT_CLK);
mcg_p->c2 = temp_reg;
/*
* MCG Control 1 register:
* - Set system clock source (MCGOUTCLK) = external reference clock
* - Set FLL external reference divider = 1024 (MCG_C1_FRDIV_32_1024)
* to get the FLL frequency of 50 MHz/1024 = 48.828KHz
* (Note: If FLL frequency must be in the in 31.25KHz-39.0625KHz
*range,
* the FLL external reference divider = 1280
*(MCG_C1_FRDIV_64_1280)
* to get 50 MHz/1280 = 39.0625KHz)
* - Select the external reference clock as the FLL reference source
*
*/
temp_reg = mcg_p->c1 &
~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK);
temp_reg |=
(MCG_C1_CLKS_EXT_REF | MCG_C1_FRDIV_32_1024 | MCG_C1_IREFS_EXT);
mcg_p->c1 = temp_reg;
/*
* Confirm that the external reference clock is the FLL reference
* source
*/
while ((mcg_p->s & MCG_S_IREFST_MASK) != 0)
;
;
/*
* Confirm the external ref. clock is the system clock source
* (MCGOUTCLK)
*/
while ((mcg_p->s & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT_REF)
;
;
/*
* Transition to PBE mode.
* Configure the PLL frequency in preparation for PEE mode.
* The goal is PEE mode with a 120 MHz system clock source (MCGOUTCLK),
* which is calculated as (oscillator clock / PLL divider) * PLL
* multiplier,
* where oscillator clock = 50MHz, PLL divider = 20 and PLL multiplier =
* 48.
*/
/*
* MCG Control 5 register:
* - Set the PLL divider
*/
temp_reg = mcg_p->c5 & ~MCG_C5_PRDIV0_MASK;
temp_reg |= FRDM_K64F_PLL_DIV_20;
mcg_p->c5 = temp_reg;
/*
* MCG Control 6 register:
* - Select PLL as output for PEE mode
* - Set the PLL multiplier
*/
temp_reg = mcg_p->c6 & ~(MCG_C6_PLLS_MASK | MCG_C6_VDIV0_MASK);
temp_reg |= (MCG_C6_PLLS_PLL | FRDM_K64F_PLL_MULT_48);
mcg_p->c6 = temp_reg;
/* Confirm that the PLL clock is selected as the PLL output */
while ((mcg_p->s & MCG_S_PLLST_MASK) == 0)
;
;
/* Confirm that the PLL has acquired lock */
while ((mcg_p->s & MCG_S_LOCK0_MASK) == 0)
;
;
/*
* Transition to PEE mode.
* MCG Control 1 register:
* - Select PLL as the system clock source (MCGOUTCLK)
*/
temp_reg = mcg_p->c1 & ~MCG_C1_CLKS_MASK;
temp_reg |= MCG_C1_CLKS_FLL_PLL;
mcg_p->c1 = temp_reg;
/* Confirm that the PLL output is the system clock source (MCGOUTCLK) */
while ((mcg_p->s & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
;
;
}
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers and the
* Kinetis UART device driver.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int fsl_frdm_k64f_init(struct device *arg)
{
ARG_UNUSED(arg);
/* System Integration module */
volatile struct K20_SIM *sim_p =
(volatile struct K20_SIM *)PERIPH_ADDR_BASE_SIM;
/* Power Mgt Control module */
volatile struct K6x_PMC *pmc_p =
(volatile struct K6x_PMC *)PERIPH_ADDR_BASE_PMC;
/* Power Mgt Control module */
volatile struct K6x_MPU *mpu_p =
(volatile struct K6x_MPU *)PERIPH_ADDR_BASE_MPU;
int oldLevel; /* old interrupt lock level */
uint32_t temp_reg;
/* disable interrupts */
oldLevel = irq_lock();
/* enable the port clocks */
sim_p->scgc5.value |= (SIM_SCGC5_PORTA_CLK_EN | SIM_SCGC5_PORTB_CLK_EN |
SIM_SCGC5_PORTC_CLK_EN | SIM_SCGC5_PORTD_CLK_EN |
SIM_SCGC5_PORTE_CLK_EN);
/* release I/O power hold to allow normal run state */
pmc_p->regsc.value |= PMC_REGSC_ACKISO_MASK;
/*
* Disable memory protection and clear slave port errors.
* Note that the K64F does not implement the optional ARMv7-M memory
* protection unit (MPU), specified by the architecture (PMSAv7), in the
* Cortex-M4 core. Instead, the processor includes its own MPU module.
*/
temp_reg = mpu_p->ctrlErrStatus.value;
temp_reg &= ~MPU_VALID_MASK;
temp_reg |= MPU_SLV_PORT_ERR_MASK;
mpu_p->ctrlErrStatus.value = temp_reg;
/* clear all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
_ScbHardFaultAllFaultsReset();
/*
* Initialize the clock dividers for:
* core and system clocks = 120 MHz (PLL/OUTDIV1)
* bus clock = 60 MHz (PLL/OUTDIV2)
* FlexBus clock = 40 MHz (PLL/OUTDIV3)
* Flash clock = 24 MHz (PLL/OUTDIV4)
*/
sim_p->clkdiv1.value = ((SIM_CLKDIV(1) << SIM_CLKDIV1_OUTDIV1_SHIFT) |
(SIM_CLKDIV(2) << SIM_CLKDIV1_OUTDIV2_SHIFT) |
(SIM_CLKDIV(3) << SIM_CLKDIV1_OUTDIV3_SHIFT) |
(SIM_CLKDIV(5) << SIM_CLKDIV1_OUTDIV4_SHIFT));
/* Initialize PLL/system clock to 120 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
DECLARE_DEVICE_INIT_CONFIG(fsl_frdm_0, "", fsl_frdm_k64f_init, NULL);
SYS_DEFINE_DEVICE(fsl_frdm_0, NULL, PRIMARY, 0);

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/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Board configuration macros for the fsl_frdm_k64f platform
*
* This header file is used to specify and describe board-level aspects for the
* 'fsl_frdm_k64f' platform.
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <misc/util.h>
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(120)
/* address bases */
#define PERIPH_ADDR_BASE_MPU 0x4000D000 /* Memory Protection Unit */
#define PERIPH_ADDR_BASE_PCR 0x40049000 /* Port and pin Configuration */
#define PERIPH_ADDR_BASE_SIM 0x40047000 /* System Integration module */
#define PERIPH_ADDR_BASE_WDOG 0x40052000 /* Watchdog Timer module */
#define PERIPH_ADDR_BASE_MCG 0x40064000 /* Multipurpose Clock Generator */
#define PERIPH_ADDR_BASE_OSC 0x40065000 /* Oscillator module */
#define PERIPH_ADDR_BASE_PMC 0x4007D000 /* Power Mgt Controller module */
/* IRQs */
#define IRQ_DMA_CHAN0 0
#define IRQ_DMA_CHAN1 1
#define IRQ_DMA_CHAN2 2
#define IRQ_DMA_CHAN3 3
#define IRQ_DMA_CHAN4 4
#define IRQ_DMA_CHAN5 5
#define IRQ_DMA_CHAN6 6
#define IRQ_DMA_CHAN7 7
#define IRQ_DMA_CHAN8 8
#define IRQ_DMA_CHAN9 9
#define IRQ_DMA_CHAN10 10
#define IRQ_DMA_CHAN11 11
#define IRQ_DMA_CHAN12 12
#define IRQ_DMA_CHAN13 13
#define IRQ_DMA_CHAN14 14
#define IRQ_DMA_CHAN15 15
#define IRQ_DMA_ERR 16
#define IRQ_MCM 17
#define IRQ_FLASH_CMD 18
#define IRQ_FLASH_COLLISION 19
#define IRQ_LOW_VOLTAGE 20
#define IRQ_LOW_LEAKAGE 21
#define IRQ_WDOG_OR_EVM 22
#define IRQ_RAND_NUM_GEN 23
#define IRQ_I2C0 24
#define IRQ_I2C1 25
#define IRQ_SPI0 26
#define IRQ_SPI1 27
#define IRQ_I2S0_TX 28
#define IRQ_I2S0_RX 29
#define IRQ_RESERVED0 30
#define IRQ_UART0_STATUS 31
#define IRQ_UART0_ERROR 32
#define IRQ_UART1_STATUS 33
#define IRQ_UART1_ERROR 34
#define IRQ_UART2_STATUS 35
#define IRQ_UART2_ERROR 36
#define IRQ_UART3_STATUS 37
#define IRQ_UART3_ERROR 38
#define IRQ_ADC0 39
#define IRQ_CMP0 40
#define IRQ_CMP1 41
#define IRQ_FTM0 42
#define IRQ_FTM1 43
#define IRQ_FTM2 44
#define IRQ_CMT 45
#define IRQ_RTC_ALARM 46
#define IRQ_RTC_SEC 47
#define IRQ_TIMER0 48
#define IRQ_TIMER1 49
#define IRQ_TIMER2 50
#define IRQ_TIMER3 51
#define IRQ_PDB 52
#define IRQ_USB_OTG 53
#define IRQ_USB_CHARGE 54
#define IRQ_RESERVED1 55
#define IRQ_DAC0 56
#define IRQ_MCG 57
#define IRQ_LOW_PWR_TIMER 58
#define IRQ_GPIO_PORTA 59
#define IRQ_GPIO_PORTB 60
#define IRQ_GPIO_PORTC 61
#define IRQ_GPIO_PORTD 62
#define IRQ_GPIO_PORTE 63
#define IRQ_SOFTWARE 64
#define IRQ_SPI2 65
#define IRQ_UART4_STATUS 66
#define IRQ_UART4_ERROR 67
#define IRQ_RESERVED2 68 /* IRQ_UART5_STATUS - UART5 not implemented */
#define IRQ_RESERVED3 69 /* IRQ_UART5_ERROR - UART5 not implemented */
#define IRQ_CMP2 70
#define IRQ_FTM3 71
#define IRQ_DAC1 72
#define IRQ_ADC1 73
#define IRQ_I2C2 74
#define IRQ_CAN0_MSG_BUF 75
#define IRQ_CAN0_BUS_OFF 76
#define IRQ_CAN0_ERROR 77
#define IRQ_CAN0_TX_WARN 78
#define IRQ_CAN0_RX_WARN 79
#define IRQ_CAN0_WAKEUP 80
#define IRQ_SDHC 81
#define IRQ_ETH_IEEE1588_TMR 82
#define IRQ_ETH_TX 83
#define IRQ_ETH_RX 84
#define IRQ_ETH_ERR_MISC 85
#ifndef _ASMLANGUAGE
#include <device.h>
#include <misc/util.h>
#include <drivers/rand32.h>
/*
* UART configuration settings
*/
#include <drivers/k20_pcr.h>
#define UART_IRQ_FLAGS 0
/* Uart console settings */
#if defined(CONFIG_UART_CONSOLE)
#define CONFIG_UART_CONSOLE_PORT PCR_PORT_B
#define CONFIG_UART_CONSOLE_PORT_RX_PIN 16
#define CONFIG_UART_CONSOLE_PORT_TX_PIN 17
#define CONFIG_UART_CONSOLE_PORT_MUX_FUNC PCR_MUX_ALT3
#define CONFIG_UART_CONSOLE_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#endif /* CONFIG_UART_CONSOLE */
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */

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/*
* Copyright (c) 2015 Intel Corporation.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Board config file
*/
#include <device.h>
#include <init.h>
#include <nanokernel.h>
#include "soc.h"
#ifdef CONFIG_UART_K20
#include <uart.h>
#include <drivers/k20_pcr.h>
#include <drivers/k20_sim.h>
#include <console/uart_console.h>
#include <serial/uart_k20_priv.h>
#if defined(CONFIG_UART_CONSOLE)
#if defined(CONFIG_PRINTK) || defined(CONFIG_STDOUT_CONSOLE)
/**
* @brief Initialize K20 serial port as console
*
* Initialize the UART port for console I/O.
*
* @param dev The UART device struct
*
* @return DEV_OK if successful, otherwise failed.
*/
static int uart_k20_console_init(struct device *dev)
{
uint32_t port;
uint32_t rxPin;
uint32_t txPin;
union K20_PCR pcr = {0}; /* Pin Control Register */
/* Port/pin ctrl module */
volatile struct K20_PORT_PCR *port_pcr_p =
(volatile struct K20_PORT_PCR *)PERIPH_ADDR_BASE_PCR;
/* UART0 Rx and Tx pin assignments */
port = CONFIG_UART_CONSOLE_PORT;
rxPin = CONFIG_UART_CONSOLE_PORT_RX_PIN;
txPin = CONFIG_UART_CONSOLE_PORT_TX_PIN;
/* Enable the UART Rx and Tx Pins */
pcr.field.mux = CONFIG_UART_CONSOLE_PORT_MUX_FUNC;
port_pcr_p->port[port].pcr[rxPin] = pcr;
port_pcr_p->port[port].pcr[txPin] = pcr;
return DEV_OK;
}
DECLARE_DEVICE_INIT_CONFIG(_uart_k20_console, "", uart_k20_console_init, NULL);
SYS_DEFINE_DEVICE(_uart_k20_console, NULL, PRIMARY,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif
#endif /* CONFIG_UART_CONSOLE */
static int uart_k20_init(struct device *dev)
{
volatile struct K20_SIM *sim = /* sys integ. ctl */
(volatile struct K20_SIM *)PERIPH_ADDR_BASE_SIM;
SIM_SCGC4_t scgc4;
ARG_UNUSED(dev);
/* Although it is possible to modify the bits through
* *sim directly, the following code saves about 20 bytes
* of ROM space, compared to direct modification.
*/
scgc4.value = sim->scgc4.value;
#ifdef CONFIG_UART_K20_PORT_0
scgc4.field.uart0_clk_en = 1;
#endif
#ifdef CONFIG_UART_K20_PORT_1
scgc4.field.uart1_clk_en = 1;
#endif
#ifdef CONFIG_UART_K20_PORT_2
scgc4.field.uart2_clk_en = 1;
#endif
#ifdef CONFIG_UART_K20_PORT_3
scgc4.field.uart3_clk_en = 1;
#endif
sim->scgc4.value = scgc4.value;
#ifdef CONFIG_UART_K20_PORT_4
sim->scgc1.field.uart4_clk_en = 1;
#endif
return DEV_OK;
}
DECLARE_DEVICE_INIT_CONFIG(_uart_k20_init, "", uart_k20_init, NULL);
SYS_DEFINE_DEVICE(_uart_k20_init, NULL, PRIMARY,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_UART_K20 */

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/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Watchdog initialization for fsl_frdm_k64f platform
*
* This module initializes the watchdog for the fsl_frdm_k64f platform.
*/
#define _ASMLANGUAGE
#include <soc.h>
#include <toolchain.h>
#include <sections.h>
_ASM_FILE_PROLOGUE
GTEXT(_WdogInit)
/* watchdog register offsets */
#define WDOG_SCTRL_HI_OFFSET 0x0
#define WDOG_UNLOCK_OFFSET 0xE
/* watchdog command words */
#define WDOG_UNLOCK_1_CMD 0xC520
#define WDOG_UNLOCK_2_CMD 0xD928
/**
*
* @brief Watchdog timer disable routine
*
* This routine will disable the watchdog timer.
*
* @return N/A
*/
SECTION_FUNC(TEXT,_WdogInit)
/*
* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!!
* There are timing requirements for the execution of the unlock process.
* Single stepping through the code will cause the CPU to reset.
*/
/*
* First unlock the watchdog so that we can write to registers.
*
* This sequence must execute within 20 clock cycles, so disable
* interrupts to keep the code atomic and ensure the timing.
*/
cpsid i
ldr r0, =PERIPH_ADDR_BASE_WDOG
movw r1, #WDOG_UNLOCK_1_CMD
strh r1, [r0, #WDOG_UNLOCK_OFFSET]
movw r1, #WDOG_UNLOCK_2_CMD
strh r1, [r0, #WDOG_UNLOCK_OFFSET]
/*
* Disable the watchdog.
*
* Writes to control/configuration registers must execute within
* 256 clock cycles after unlocking.
*/
ldrh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
mov r2, #1
bics r1, r2
strh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
cpsie i
bx lr

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# Kconfig - TI LM3S6965 platform configuration options
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_TI_LM3S6965
config SOC
default ti_lm3s6965
config NUM_IRQ_PRIO_BITS
int
default 3
config NUM_IRQS
int
# must be >= the highest interrupt number used
# - include the UART interrupts
default 34
config SOC_TI_LM3S6965_QEMU
def_bool y
# Platform has only been tested on QEMU, not on real hardware, so always
# assume it is used for a QEMU target.
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 12000000
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
config IPM_CONSOLE_PRIORITY
default 60
if UART_STELLARIS
config UART_STELLARIS_PORT_0
def_bool y
if UART_STELLARIS_PORT_0
config UART_STELLARIS_PORT_0_BASE_ADDR
default 0x4000C000
config UART_STELLARIS_PORT_0_IRQ
default 6
config UART_STELLARIS_PORT_0_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_0_CLK_FREQ
default 12000000
endif
config UART_STELLARIS_PORT_1
def_bool y
if UART_STELLARIS_PORT_1
config UART_STELLARIS_PORT_1_BASE_ADDR
default 0x4000D000
config UART_STELLARIS_PORT_1_IRQ
default 6
config UART_STELLARIS_PORT_1_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_1_CLK_FREQ
default 12000000
endif
config UART_STELLARIS_PORT_2
def_bool y
if UART_STELLARIS_PORT_2
config UART_STELLARIS_PORT_2_BASE_ADDR
default 0x4000E000
config UART_STELLARIS_PORT_2_IRQ
default 33
config UART_STELLARIS_PORT_2_BAUD_RATE
default 115200
config UART_STELLARIS_PORT_2_CLK_FREQ
default 12000000
endif
endif # UART_STELLARIS
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
config UART_CONSOLE_IRQ
default 5
config UART_CONSOLE_IRQ_PRI
default 3
endif
if BLUETOOTH_UART
config BLUETOOTH_UART_ON_DEV_NAME
default "UART_1"
config BLUETOOTH_UART_IRQ
default 6
config BLUETOOTH_UART_IRQ_PRI
default 3
endif
if UART_PIPE
config UART_PIPE_ON_DEV_NAME
default "UART_2"
config UART_PIPE_IRQ
default 33
config UART_PIPE_IRQ_PRI
default 3
endif
endif

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config SOC_TI_LM3S6965
bool "TI LM3S6965"
select CPU_CORTEX_M
select CPU_CORTEX_M3

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obj-y += soc_config.o
obj-y += soc.o
obj-y += nmi_on_reset.o
obj-y += scp.o
obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o

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/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief IRQ part of vector table
*
* This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases:
*
* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
* binds _isr_wrapper() to all the IRQ entries in the vector table.
*
* b) When the platform is written so that device ISRs are installed directly in
* the vector table, they are enumerated here.
*/
#include <toolchain.h>
#include <sections.h>
#if defined(CONFIG_CONSOLE_HANDLER)
#include <soc.h>
#include <console/uart_console.h>
#endif /* CONFIG_CONSOLE_HANDLER */
#if defined(CONFIG_BLUETOOTH_UART)
#include <soc.h>
#include <bluetooth/uart.h>
#endif /* CONFIG_BLUETOOTH_UART */
extern void _isr_wrapper(void);
typedef void (*vth)(void); /* Vector Table Handler */
#if defined(CONFIG_SW_ISR_TABLE)
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _isr_wrapper,
};
#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
extern void _irq_spurious(void);
#if defined(CONFIG_CONSOLE_HANDLER)
static void _uart_console_isr(void)
{
uart_console_isr(NULL);
_IntExit();
}
#endif /* CONFIG_CONSOLE_HANDLER */
#if defined(CONFIG_BLUETOOTH_UART)
static void _bt_uart_isr(void)
{
bt_uart_isr(NULL);
_IntExit();
}
#endif /* CONFIG_BLUETOOTH_UART */
/* placeholders: fill with real ISRs */
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS] = {
[0 ...(CONFIG_NUM_IRQS - 1)] = _irq_spurious,
#if defined(CONFIG_CONSOLE_HANDLER)
[CONFIG_UART_CONSOLE_IRQ] = _uart_console_isr,
#endif
#if defined(CONFIG_BLUETOOTH_UART)
[CONFIG_BLUETOOTH_UART_IRQ] = _bt_uart_isr,
#endif
};
#endif /* CONFIG_SW_ISR_TABLE */

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/* linker.cmd - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <arch/arm/cortex_m/scripts/linker.cmd>

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arch/arm/soc/ti_lm3s6965/nmi_on_reset.S Normal file
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/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Default basic NMI handler before the kernel is up
*
* Provide a default handler for NMI before the system is up. The default action
* is to hard hang, sleeping.
*
* This might be preferable than rebooting to help debugging, or because
* rebooting might trigger the exact same problem over and over.
*/
#define _ASMLANGUAGE
#include <toolchain.h>
#include <sections.h>
_ASM_FILE_PROLOGUE
GTEXT(_SysNmiOnReset)
SECTION_FUNC(TEXT, _SysNmiOnReset)
wfi
b _SysNmiOnReset

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/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief TI LM3S6965 System Control Peripherals interface
*
*
* Library for controlling target-specific devices present in the 0x400fe000
* peripherals memory region.
*
* Currently, only enabling the main OSC with default value is implemented.
*/
#include <stdint.h>
#include <toolchain.h>
#include <sections.h>
#include "scp.h"
/* System Control Peripheral (SCP) Registers */
volatile struct __scp __scp_section __scp;
/**
*
* @brief Enable main oscillator with default frequency of 6MHz
*
* @return N/A
*/
void _ScpMainOscEnable(void)
{
union __rcc reg;
reg.value = __scp.clock.rcc.value;
reg.bit.moscdis = 0;
reg.bit.oscsrc = _SCP_OSC_SOURCE_MAIN;
reg.bit.xtal = _SCP_CRYSTAL_6MHZ;
__scp.clock.rcc.value = reg.value;
}

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/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief TI LM3S6965 System Control Peripherals interface
*
* This module defines the System Control Peripheral Registers for TI LM3S6965
* processor. The registers defined are in region 0x400fe000.
*
* System Control 0x400fe000
*
* These modules are not defined:
*
* Hibernation Module 0x400fc000
* Internal Memory 0x400fd000
* Hibernation Module 0x400fc000
*
* The registers and bit field names are taken from the 'Stellaris LM3S6965
* Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document,
* section 5.4/5.5, pp .184-200.
*/
#ifndef _SCP_H_
#define _SCP_H_
#include <stdint.h>
#define _SCP_OSC_SOURCE_MAIN 0
#define _SCP_OSC_SOURCE_INTERNAL 1
#define _SCP_OSC_SOURCE_INTERNAL_DIV4 2
#define _SCP_OSC_SOURCE_INTERNAL_20KHZ 3
#define _SCP_OSC_SOURCE_EXTERNAL_32KHZ 7 /* Valid with RCC2 only */
#define _SCP_CRYSTAL_1MHZ_NOPLL 0
#define _SCP_CRYSTAL_1_8432MHZ_NOPLL 1
#define _SCP_CRYSTAL_2MHZ_NOPLL 2
#define _SCP_CRYSTAL_2_4576MHZ_NOPLL 3
#define _SCP_CRYSTAL_3_579545MHZ 4
#define _SCP_CRYSTAL_3_6864MHZ 5
#define _SCP_CRYSTAL_4MHZ 6
#define _SCP_CRYSTAL_4_0964MHZ 7
#define _SCP_CRYSTAL_4_9152MHZ 8
#define _SCP_CRYSTAL_5MHZ 9
#define _SCP_CRYSTAL_5_12MHZ 10
#define _SCP_CRYSTAL_6MHZ 11 /* reset value */
#define _SCP_CRYSTAL_6_144MHZ 12
#define _SCP_CRYSTAL_7_3728MHZ 13
#define _SCP_CRYSTAL_8MHZ 14
#define _SCP_CRYSTAL_8_192MHZ 15
union __rcc {
uint32_t value;
struct {
uint32_t moscdis : 1 __packed;
uint32_t ioscdis : 1 __packed;
uint32_t rsvd__2_3 : 2 __packed;
uint32_t oscsrc : 2 __packed;
uint32_t xtal : 4 __packed;
uint32_t rsvd__10 : 1 __packed;
uint32_t bypass : 1 __packed;
uint32_t rsvd__12 : 1 __packed;
uint32_t pwrdn : 1 __packed;
uint32_t rsvd__14_16 : 3 __packed;
uint32_t pwmdiv : 3 __packed; /* 2**(n+1) */
uint32_t usepwmdiv : 1 __packed;
uint32_t rsvd__21 : 1 __packed;
uint32_t usesysdiv : 1 __packed;
uint32_t sysdiv : 4 __packed;
uint32_t acg : 1 __packed;
uint32_t rsvd__28_31 : 4 __packed;
} bit;
};
union __rcc2 {
uint32_t value;
struct {
uint8_t rsvd__0_3 : 4 __packed;
uint8_t oscsrc2 : 3 __packed;
uint16_t rsvd__7_10 : 4 __packed;
uint8_t bypass2 : 1 __packed;
uint8_t rsvd__12 : 1 __packed;
uint8_t pwrdn2 : 1 __packed;
uint16_t rsvd__14_22 : 9 __packed;
uint16_t sysdiv2 : 6 __packed;
uint8_t rsvd__29_30 : 2 __packed;
uint8_t usercc2 : 1 __packed;
} bit;
};
struct __scp {
uint32_t did0; /* 0x000 RO Device ID*/
uint32_t did1; /* 0x004 RO Device ID*/
uint32_t dc0; /* 0x008 RO Device Capabilities */
uint32_t dc1; /* 0x00c RO Device Capabilities */
uint32_t dc2; /* 0x010 RO Device Capabilities */
uint32_t dc3; /* 0x014 RO Device Capabilities */
uint32_t dc4; /* 0x018 RO Device capabilities */
uint32_t rsvd__01c_02f[(0x30 - 0x1c) / 4];
uint32_t pborctl; /* 0x030 RW Brown-Out Reset ConTroL */
uint32_t ldopctl; /* 0x034 RW LDO Power ConTroL */
uint32_t rsvd__038_03f[(0x40 - 0x38) / 4];
uint32_t srcr0; /* 0x040 RW Software Reset Control Register */
uint32_t srcr1; /* 0x044 RW Software Reset Control Register */
uint32_t srcr2; /* 0x048 RW Software Reset Control Register */
uint32_t rsvd__04c_04f;
uint32_t ris; /* 0x050 RO Raw Interrupt Status */
uint32_t imc; /* 0x054 RW Interrupt Mask Control */
uint32_t misc; /* 0x058 RW1C Masked Int. Status & Clear */
uint32_t resc; /* 0x05C RW RESet Cause */
struct {
union __rcc rcc; /* 0x060 RW Run-mode Clock Configuration */
uint32_t pllcfg; /* 0x064 RW xtal-to-pll translation */
uint32_t rsvd__068_06f[(0x70 - 0x068) / 4];
union __rcc2 rcc2; /* 0x070 RW Run-mode Clock Configuration */
uint32_t rsvd__074_0ff[(0x100 - 0x074) / 4];
uint32_t rcgc0; /* 0x100 RW Run-mode Clock Gating */
uint32_t rcgc1; /* 0x104 RW Run-mode Clock Gating */
uint32_t rcgc2; /* 0x108 RW Run-mode Clock Gating */
uint32_t rsvd__10c_10f;
uint32_t scgc0; /* 0x110 RW Sleep-mode Clock Gating */
uint32_t scgc1; /* 0x114 RW Sleep-mode Clock Gating */
uint32_t scgc2; /* 0x118 RW Sleep-mode Clock Gating */
uint32_t rsvd__11c_11f;
uint32_t dcgc0; /* 0x120 RW Deep sleep mode Clock Gating */
uint32_t dcgc1; /* 0x124 RW Deep sleep mode Clock Gating */
uint32_t dcgc2; /* 0x128 RW Deep sleep mode Clock Gating */
uint32_t rsvd__12c_143[(0x144 - 0x12c) / 4];
uint32_t
dslpclkcfg; /* 0x144 RW Deep SLeeP CLocK ConFiGuration
*/
} clock;
};
extern volatile struct __scp __scp;
#endif /* _SCP_H_ */

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/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief System/hardware module for ti_lm3s6965 platform
*
* This module provides routines to initialize and support board-level hardware
* for the ti_lm3s6965 platform.
*/
#include <nanokernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#ifdef CONFIG_RUNTIME_NMI
extern void _NmiInit(void);
#define NMI_INIT() _NmiInit()
#else
#define NMI_INIT()
#endif
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers and the
* integrated 16550-compatible UART device driver.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int ti_lm3s6965_init(struct device *arg)
{
ARG_UNUSED(arg);
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
return 0;
}
DECLARE_DEVICE_INIT_CONFIG(ti_lm3_0, "", ti_lm3s6965_init, NULL);
SYS_DEFINE_DEVICE(ti_lm3_0, NULL, PRIMARY,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Board configuration macros for the QEMU for arm platform
*
* This header file is used to specify and describe board-level aspects for
* the 'QEMU' platform.
*/
#ifndef _BOARD__H_
#define _BOARD__H_
#include <misc/util.h>
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
/* IRQs */
#define IRQ_GPIO_PORTA 0
#define IRQ_GPIO_PORTB 1
#define IRQ_GPIO_PORTC 2
#define IRQ_GPIO_PORTD 3
#define IRQ_GPIO_PORTE 4
#define IRQ_UART0 5
#define IRQ_UART1 6
#define IRQ_SSI0 7
#define IRQ_I2C0 8
#define IRQ_PWM_FAULT 9
#define IRQ_PWM_GEN0 10
#define IRQ_PWM_GEN1 11
#define IRQ_PWM_GEN2 12
#define IRQ_QEI0 13
#define IRQ_ADC0_SEQ0 14
#define IRQ_ADC0_SEQ1 15
#define IRQ_ADC0_SEQ2 16
#define IRQ_ADC0_SEQ3 17
#define IRQ_WDOG0 18
#define IRQ_TIMER0A 19
#define IRQ_TIMER0B 20
#define IRQ_TIMER1A 21
#define IRQ_TIMER1B 22
#define IRQ_TIMER2A 23
#define IRQ_TIMER2B 24
#define IRQ_ANALOG_COMP0 25
#define IRQ_ANALOG_COMP1 26
#define IRQ_RESERVED0 27
#define IRQ_SYS_CONTROL 28
#define IRQ_FLASH_MEM_CTRL 29
#define IRQ_GPIO_PORTF 30
#define IRQ_GPIO_PORTG 31
#define IRQ_RESERVED1 32
#define IRQ_UART2 33
#define IRQ_RESERVED2 34
#define IRQ_TIMER3A 35
#define IRQ_TIMER3B 36
#define IRQ_I2C1 37
#define IRQ_QEI1 38
#define IRQ_RESERVED3 39
#define IRQ_RESERVED4 40
#define IRQ_RESERVED5 41
#define IRQ_ETH 42
#define IRQ_HIBERNATION 43
#ifndef _ASMLANGUAGE
#include <device.h>
#include <misc/util.h>
#include <drivers/rand32.h>
/* uart configuration settings */
#define UART_IRQ_FLAGS 0
#endif /* !_ASMLANGUAGE */
#endif /* _BOARD__H_ */

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/*
* Copyright (c) 2015 Intel Corporation.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Board config file
*/
#include <device.h>
#include <init.h>
#include <nanokernel.h>
#include "soc.h"
#ifdef CONFIG_UART_STELLARIS
#include <uart.h>
#define RCGC1 (*((volatile uint32_t *)0x400FE104))
#define RCGC1_UART0_EN 0x00000001
#define RCGC1_UART1_EN 0x00000002
#define RCGC1_UART2_EN 0x00000004
static int uart_stellaris_init(struct device *dev)
{
#ifdef CONFIG_UART_STELLARIS_PORT_0
RCGC1 |= RCGC1_UART0_EN;
#endif
#ifdef CONFIG_UART_STELLARIS_PORT_1
RCGC1 |= RCGC1_UART1_EN;
#endif
#ifdef CONFIG_UART_STELLARIS_PORT_2
RCGC1 |= RCGC1_UART2_EN;
#endif
return DEV_OK;
}
DECLARE_DEVICE_INIT_CONFIG(_uart_stellaris_en, "", uart_stellaris_init, NULL);
SYS_DEFINE_DEVICE(_uart_stellaris_en, NULL, PRIMARY,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
#endif /* CONFIG_UART_STELLARIS */