Bluetooth: Controller: nRF54Lx: Support Radio fast ramp up

Add support for Radio fast ramp up for nRF54Lx SoCs.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
This commit is contained in:
Vinayak Kariappa Chettimada 2024-06-10 22:18:19 +02:00 committed by Anas Nashif
commit 10a466f31f
10 changed files with 56 additions and 37 deletions

View file

@ -865,7 +865,8 @@ config BT_CTLR_NRF_GRTC_AUTOEN_DEFAULT
config BT_CTLR_RADIO_ENABLE_FAST
bool "Use tTXEN/RXEN,FAST ramp-up"
depends on SOC_COMPATIBLE_NRF52X || SOC_COMPATIBLE_NRF53X
depends on SOC_COMPATIBLE_NRF52X || SOC_COMPATIBLE_NRF53X || SOC_SERIES_NRF54LX
select BT_CTLR_SW_SWITCH_SINGLE_TIMER if SOC_SERIES_NRF54LX
default y
help
Enable use of fast radio ramp-up mode.
@ -879,7 +880,8 @@ config BT_CTLR_TIFS_HW
config BT_CTLR_SW_SWITCH_SINGLE_TIMER
bool "Single TIMER tIFS Trx SW switching"
depends on (!BT_CTLR_TIFS_HW) && (SOC_COMPATIBLE_NRF52X || SOC_COMPATIBLE_NRF53X)
depends on (!BT_CTLR_TIFS_HW) && (SOC_COMPATIBLE_NRF52X || SOC_COMPATIBLE_NRF53X || \
SOC_SERIES_NRF54LX)
help
Implement the tIFS Trx SW switch with the same TIMER
instance, as the one used for BLE event timing. Requires

View file

@ -243,8 +243,13 @@ void radio_reset(void)
#endif
#if defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
NRF_RADIO->TIMING = (0U << RADIO_TIMING_RU_Pos) &
#if defined(CONFIG_BT_CTLR_TIFS_HW)
NRF_RADIO->TIMING = (RADIO_TIMING_RU_Legacy << RADIO_TIMING_RU_Pos) &
RADIO_TIMING_RU_Msk;
#else /* !CONFIG_BT_CTLR_TIFS_HW */
NRF_RADIO->TIMING = (RADIO_TIMING_RU_Fast << RADIO_TIMING_RU_Pos) &
RADIO_TIMING_RU_Msk;
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
NRF_POWER->TASKS_CONSTLAT = 1U;
#endif /* CONFIG_SOC_COMPATIBLE_NRF54LX */
@ -949,13 +954,13 @@ void sw_switch(uint8_t dir_curr, uint8_t dir_next, uint8_t phy_curr, uint8_t fla
* time-stamp.
*/
hal_radio_end_time_capture_ppi_config();
#if !defined(CONFIG_SOC_COMPATIBLE_NRF53X)
#if !defined(CONFIG_SOC_COMPATIBLE_NRF53X) && !defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
/* The function is not called for nRF5340 single timer configuration because
* HAL_SW_SWITCH_TIMER_CLEAR_PPI is equal to HAL_RADIO_END_TIME_CAPTURE_PPI,
* so channel is already enabled.
*/
hal_radio_nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI));
#endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
#endif /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
#endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
sw_tifs_toggle += 1U;
@ -1802,12 +1807,14 @@ void radio_tmr_end_capture(void)
* hal_sw_switch_timer_clear_ppi_config() and sw_switch(). There is no need to
* configure the channel again in this function.
*/
#if !defined(CONFIG_SOC_COMPATIBLE_NRF53X) || \
(defined(CONFIG_SOC_COMPATIBLE_NRF53X) && !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER))
#if (!defined(CONFIG_SOC_COMPATIBLE_NRF53X) && !defined(CONFIG_SOC_COMPATIBLE_NRF54LX)) || \
((defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)) && \
!defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER))
hal_radio_end_time_capture_ppi_config();
hal_radio_nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI));
#endif /* !CONFIG_SOC_COMPATIBLE_NRF53X ||
* (CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
#endif /* (!CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX) ||
* ((CONFIG_SOC_COMPATIBLE_NRF53X || CONFIG_SOC_COMPATIBLE_NRF54LX) &&
* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
*/
}

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@ -377,7 +377,9 @@ void radio_df_cte_rx_4us_switching(bool cte_info_in_s1, uint8_t phy)
void radio_df_ant_switch_pattern_clear(void)
{
NRF_RADIO->CLEARPATTERN = RADIO_CLEARPATTERN_CLEARPATTERN_Clear;
NRF_RADIO->CLEARPATTERN = (HAL_RADIO_CLEARPATTERN_CLEARPATTERN_Clear <<
RADIO_CLEARPATTERN_CLEARPATTERN_Pos) &
RADIO_CLEARPATTERN_CLEARPATTERN_Msk;
}
void radio_df_reset(void)

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@ -343,9 +343,10 @@
#endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
/* HAL abstraction of Radio bitfields */
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_CLEARPATTERN_CLEARPATTERN_Clear RADIO_CLEARPATTERN_CLEARPATTERN_Clear
/* HAL abstraction of Radio IRQ number */
#define HAL_RADIO_IRQn RADIO_IRQn

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@ -343,9 +343,10 @@
#endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
/* HAL abstraction of Radio bitfields */
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_CLEARPATTERN_CLEARPATTERN_Clear RADIO_CLEARPATTERN_CLEARPATTERN_Clear
/* HAL abstraction of Radio IRQ number */
#define HAL_RADIO_IRQn RADIO_IRQn

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@ -343,9 +343,10 @@
#endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
/* HAL abstraction of Radio bitfields */
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_CLEARPATTERN_CLEARPATTERN_Clear RADIO_CLEARPATTERN_CLEARPATTERN_Clear
/* HAL abstraction of Radio IRQ number */
#define HAL_RADIO_IRQn RADIO_IRQn

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@ -365,9 +365,10 @@
#endif
/* HAL abstraction of Radio bitfields */
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_END_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_CLEARPATTERN_CLEARPATTERN_Clear RADIO_CLEARPATTERN_CLEARPATTERN_Clear
/* HAL abstraction of Radio IRQ number */
#define HAL_RADIO_IRQn RADIO_IRQn

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@ -9,16 +9,22 @@
#define NRF_RTC NRF_RTC10
#endif /* !CONFIG_BT_CTLR_NRF_GRTC */
#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
#error "Single Timer feature not supported yet"
#endif
#undef EVENT_TIMER_ID
#define EVENT_TIMER_ID 10
#undef EVENT_TIMER
#define EVENT_TIMER _CONCAT(NRF_TIMER, EVENT_TIMER_ID)
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
#undef SW_SWITCH_TIMER
#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
#define SW_SWITCH_TIMER EVENT_TIMER
#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
/* TODO: Using NRF_TIMER from another domain needs DPPIC and PPIB setup */
#error "SW tIFS switching using dedicated second timer not supported yet."
#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
/* HAL abstraction of event timer prescaler value */
#define HAL_EVENT_TIMER_PRESCALER_VALUE 5U
@ -355,9 +361,10 @@
#endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
/* HAL abstraction of Radio bitfields */
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET00_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_INTENSET_DISABLED_Msk RADIO_INTENSET00_DISABLED_Msk
#define HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk RADIO_SHORTS_PHYEND_DISABLE_Msk
#define HAL_RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL)
/* HAL abstraction of Radio IRQ number */
#define HAL_RADIO_IRQn RADIO_0_IRQn

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@ -168,7 +168,6 @@ static inline void hal_trigger_rateoverride_ppi_config(void)
nrf_ccm_subscribe_set(NRF_CCM, NRF_CCM_TASK_RATEOVERRIDE, HAL_TRIGGER_RATEOVERRIDE_PPI);
}
#endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
#endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
/*******************************************************************************
@ -195,6 +194,7 @@ static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void)
nrf_ccm_subscribe_set(NRF_CCM, NRF_CCM_TASK_CRYPT, HAL_TRIGGER_CRYPT_DELAY_PPI);
}
#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
#endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
/******************************************************************************/
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
@ -203,10 +203,10 @@ static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void)
#define NRF_RADIO_PUBLISH_PDU_END_EVT PUBLISH_PHYEND
/* Wrappenr for EVENTS_END event name used by nRFX API */
#define NRFX_RADIO_TXRX_END_EVENT NRF_RADIO_EVENT_PHYEND
#else
#else /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
#define NRF_RADIO_PUBLISH_PDU_END_EVT PUBLISH_END
#define NRFX_RADIO_TXRX_END_EVENT NRF_RADIO_EVENT_END
#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
#endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
/* DPPI setup used for SW-based auto-switching during TIFS. */

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@ -3,7 +3,6 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#if defined(CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET) || defined(DPPI_PRESENT)
/*******************************************************************************
* Enable Radio on Event Timer tick:
@ -98,9 +97,9 @@
*/
#if !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI 24
#else
#else /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
#define HAL_SW_SWITCH_TIMER_CLEAR_PPI HAL_RADIO_END_TIME_CAPTURE_PPI
#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
#endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
/* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
* to a PPI GROUP TASK DISABLE task (PPI group with index <index>).
@ -167,5 +166,3 @@
*/
#define SW_SWITCH_TIMER_TASK_GROUP_BASE 0
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
#endif /* CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET || DPPI_PRESENT */