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interrupt_controller: sam0: Add support for SAME54

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The EIC/PORT peripheral works very much alike the one in
previous sam0 parts.

Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
This commit is contained in:
Benjamin Valentin 2019-05-07 15:06:25 +02:00 • committed by Andrew Boie
commit 10a1b25da6
1 changed files with 29 additions and 6 deletions
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35
drivers/interrupt_controller/sam0_eic.c
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@ -33,8 +33,22 @@ DEVICE_DECLARE(sam0_eic);
static void wait_synchronization(void)
{
#ifdef REG_EIC_SYNCBUSY
while (EIC->SYNCBUSY.reg) {
}
#else
while (EIC->STATUS.bit.SYNCBUSY) {
}
#endif
}
static inline void set_eic_enable(bool on)
{
#ifdef REG_EIC_CTRLA
EIC->CTRLA.bit.ENABLE = on;
#else
EIC->CTRL.bit.ENABLE = on;
#endif
}
static void sam0_eic_isr(void *arg)
@ -109,7 +123,7 @@ int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
/* Lock everything so it's safe to reconfigure */
key = irq_lock();
/* Disable the EIC for reconfiguration */
EIC->CTRL.bit.ENABLE = 0;
set_eic_enable(0);
line_assignment = &dev_data->lines[line_index];
@ -156,7 +170,7 @@ int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
/* Apply the config to the EIC itself */
EIC->CONFIG[config_index].reg = config;
EIC->CTRL.bit.ENABLE = 1;
set_eic_enable(1);
wait_synchronization();
/*
* Errata: The EIC generates a spurious interrupt for the newly
@ -168,7 +182,7 @@ int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
return 0;
err_in_use:
EIC->CTRL.bit.ENABLE = 1;
set_eic_enable(1);
wait_synchronization();
irq_unlock(key);
return -EBUSY;
@ -215,7 +229,7 @@ int sam0_eic_release(int port, int pin)
/* Lock everything so it's safe to reconfigure */
key = irq_lock();
/* Disable the EIC */
EIC->CTRL.bit.ENABLE = 0;
set_eic_enable(0);
wait_synchronization();
/*
@ -236,7 +250,7 @@ int sam0_eic_release(int port, int pin)
EIC->INTFLAG.reg = mask;
done:
EIC->CTRL.bit.ENABLE = 1;
set_eic_enable(1);
wait_synchronization();
irq_unlock(key);
return 0;
@ -326,12 +340,21 @@ static int sam0_eic_init(struct device *dev)
{
ARG_UNUSED(dev);
#ifdef MCLK
/* Enable the EIC clock in APBAMASK */
MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
/* Enable the GCLK */
GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0 |
GCLK_PCHCTRL_CHEN;
#else
/* Enable the EIC clock in PM */
PM->APBAMASK.bit.EIC_ = 1;
/* Enable the GCLK */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_CLKEN;
#endif
#ifdef DT_INST_0_ATMEL_SAM0_EIC_IRQ_0
SAM0_EIC_IRQ_CONNECT(0);
@ -382,7 +405,7 @@ static int sam0_eic_init(struct device *dev)
SAM0_EIC_IRQ_CONNECT(15);
#endif
EIC->CTRL.bit.ENABLE = 1;
set_eic_enable(1);
wait_synchronization();
return 0;