drivers: spi: Update MCUX Flexcomm driver to add DMA support
Add DMA support to the MCUX Flexcomm SPI driver Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
Mahesh Mahadevan
Kumar Gala
parent
da3e834d58
commit
10809b5402
3 changed files with 479 additions and 13 deletions
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@ -1,5 +1,5 @@
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# Copyright (c) 2016, Freescale Semiconductor, Inc.
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# Copyright (c) 2017,2019, NXP
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# Copyright (c) 2017-2020, NXP
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# SPDX-License-Identifier: Apache-2.0
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config SPI_MCUX_FLEXCOMM
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@ -7,3 +7,12 @@ config SPI_MCUX_FLEXCOMM
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depends on HAS_MCUX_FLEXCOMM
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help
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Enable support for mcux flexcomm spi driver.
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if SPI_MCUX_FLEXCOMM
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config SPI_MCUX_FLEXCOMM_DMA
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bool "MCUX FLEXCOMM SPI DMA Support"
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select DMA
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help
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Enable the SPI DMA mode for SPI instances
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that enable dma channels in their device tree node.
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endif # SPI_MCUX_FLEXCOMM
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@ -12,6 +12,9 @@
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#include <drivers/clock_control.h>
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#include <fsl_spi.h>
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#include <logging/log.h>
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#ifdef CONFIG_SPI_MCUX_FLEXCOMM_DMA
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#include <drivers/dma.h>
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#endif
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LOG_MODULE_REGISTER(spi_mcux_flexcomm, CONFIG_SPI_LOG_LEVEL);
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@ -27,12 +30,37 @@ struct spi_mcux_config {
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void (*irq_config_func)(const struct device *dev);
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};
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#ifdef CONFIG_SPI_MCUX_FLEXCOMM_DMA
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#define SPI_MCUX_FLEXCOMM_DMA_ERROR_FLAG 0x01
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#define SPI_MCUX_FLEXCOMM_DMA_RX_DONE_FLAG 0x02
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#define SPI_MCUX_FLEXCOMM_DMA_TX_DONE_FLAG 0x04
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#define SPI_MCUX_FLEXCOMM_DMA_DONE_FLAG \
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(SPI_MCUX_FLEXCOMM_DMA_RX_DONE_FLAG | SPI_MCUX_FLEXCOMM_DMA_TX_DONE_FLAG)
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struct stream {
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const char *dma_name;
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const struct device *dma_dev;
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uint32_t channel; /* stores the channel for dma */
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struct dma_config dma_cfg;
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struct dma_block_config dma_blk_cfg[2];
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};
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#endif
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struct spi_mcux_data {
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const struct device *dev;
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const struct device *dev_clock;
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spi_master_handle_t handle;
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struct spi_context ctx;
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size_t transfer_len;
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#ifdef CONFIG_SPI_MCUX_FLEXCOMM_DMA
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volatile uint32_t status_flags;
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struct stream dma_rx;
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struct stream dma_tx;
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/* dummy value used for transferring NOP when tx buf is null */
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uint32_t dummy_tx_buffer;
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/* Used to send the last word */
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uint32_t last_word;
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#endif
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};
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static void spi_mcux_transfer_next_packet(const struct device *dev)
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@ -184,7 +212,6 @@ static int spi_mcux_configure(const struct device *dev,
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SPI_MasterTransferCreateHandle(base, &data->handle,
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spi_mcux_transfer_callback, data);
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SPI_SetDummyData(base, 0);
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data->ctx.config = spi_cfg;
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@ -222,6 +249,369 @@ static int spi_mcux_configure(const struct device *dev,
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return 0;
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}
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#ifdef CONFIG_SPI_MCUX_FLEXCOMM_DMA
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/* Dummy buffer used as a sink when rc buf is null */
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uint32_t dummy_rx_buffer;
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/* This function is executed in the interrupt context */
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static void spi_mcux_dma_callback(const struct device *dev, void *arg,
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uint32_t channel, int status)
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{
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/* arg directly holds the spi device */
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struct spi_mcux_data *data = arg;
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if (status != 0) {
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LOG_ERR("DMA callback error with channel %d.", channel);
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data->status_flags |= SPI_MCUX_FLEXCOMM_DMA_ERROR_FLAG;
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} else {
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/* identify the origin of this callback */
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if (channel == data->dma_tx.channel) {
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/* this part of the transfer ends */
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data->status_flags |= SPI_MCUX_FLEXCOMM_DMA_TX_DONE_FLAG;
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} else if (channel == data->dma_rx.channel) {
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/* this part of the transfer ends */
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data->status_flags |= SPI_MCUX_FLEXCOMM_DMA_RX_DONE_FLAG;
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} else {
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LOG_ERR("DMA callback channel %d is not valid.",
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channel);
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data->status_flags |= SPI_MCUX_FLEXCOMM_DMA_ERROR_FLAG;
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}
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}
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spi_context_complete(&data->ctx, 0);
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}
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static void spi_mcux_prepare_txlastword(uint32_t *txLastWord,
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const uint8_t *buf, const struct spi_config *spi_cfg,
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size_t len)
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{
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uint32_t word_size;
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if (word_size > 8) {
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*txLastWord = (((uint32_t)buf[len - 1U] << 8U) |
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(buf[len - 2U]));
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} else {
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*txLastWord = buf[len - 1U];
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}
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*txLastWord |= (uint32_t)SPI_FIFOWR_EOT_MASK;
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*txLastWord |= ((uint32_t)SPI_DEASSERT_ALL &
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(~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)spi_cfg->slave)));
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/* set width of data - range asserted at entry */
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*txLastWord |= SPI_FIFOWR_LEN(word_size - 1);
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}
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static void spi_mcux_prepare_txdummy(uint32_t *dummy, bool last_packet,
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const struct spi_config *spi_cfg)
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{
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uint32_t word_size;
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if (last_packet) {
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*dummy |= (uint32_t)SPI_FIFOWR_EOT_MASK;
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}
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*dummy |= ((uint32_t)SPI_DEASSERT_ALL &
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(~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)spi_cfg->slave)));
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/* set width of data - range asserted at entry */
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*dummy |= SPI_FIFOWR_LEN(word_size - 1);
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}
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static int spi_mcux_dma_tx_load(const struct device *dev, const uint8_t *buf,
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const struct spi_config *spi_cfg, size_t len, bool last_packet)
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{
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const struct spi_mcux_config *cfg = dev->config;
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struct spi_mcux_data *data = dev->data;
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struct dma_block_config *blk_cfg;
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int ret;
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SPI_Type *base = cfg->base;
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uint32_t word_size;
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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/* remember active TX DMA channel (used in callback) */
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struct stream *stream = &data->dma_tx;
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blk_cfg = &stream->dma_blk_cfg[0];
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/* prepare the block for this TX DMA channel */
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memset(blk_cfg, 0, sizeof(struct dma_block_config));
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/* tx direction has memory as source and periph as dest. */
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if (buf == NULL) {
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data->dummy_tx_buffer = 0;
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data->last_word = 0;
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spi_mcux_prepare_txdummy(&data->dummy_tx_buffer, last_packet, spi_cfg);
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if (last_packet &&
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((word_size > 8) ? (len > 2U) : (len > 1U))) {
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spi_mcux_prepare_txdummy(&data->last_word, last_packet, spi_cfg);
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blk_cfg->source_gather_en = 1;
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blk_cfg->source_address = (uint32_t)&data->dummy_tx_buffer;
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blk_cfg->dest_address = (uint32_t)&base->FIFOWR;
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blk_cfg->block_size = (word_size > 8) ?
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(len - 2U) : (len - 1U);
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blk_cfg->next_block = &stream->dma_blk_cfg[1];
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blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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blk_cfg = &stream->dma_blk_cfg[1];
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/* prepare the block for this TX DMA channel */
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memset(blk_cfg, 0, sizeof(struct dma_block_config));
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blk_cfg->source_address = (uint32_t)&data->last_word;
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blk_cfg->dest_address = (uint32_t)&base->FIFOWR;
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blk_cfg->block_size = sizeof(uint32_t);
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blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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} else {
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blk_cfg->source_address = (uint32_t)&data->dummy_tx_buffer;
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blk_cfg->dest_address = (uint32_t)&base->FIFOWR;
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blk_cfg->block_size = len;
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blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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} else {
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if (last_packet) {
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spi_mcux_prepare_txlastword(&data->last_word, buf, spi_cfg, len);
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}
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/* If last packet and data transfer frame is bigger then 1,
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* use dma descriptor to send the last data.
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*/
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if (last_packet &&
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((word_size > 8) ? (len > 2U) : (len > 1U))) {
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blk_cfg->source_gather_en = 1;
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blk_cfg->source_address = (uint32_t)buf;
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blk_cfg->dest_address = (uint32_t)&base->FIFOWR;
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blk_cfg->block_size = (word_size > 8) ?
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(len - 2U) : (len - 1U);
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blk_cfg->next_block = &stream->dma_blk_cfg[1];
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blk_cfg = &stream->dma_blk_cfg[1];
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/* prepare the block for this TX DMA channel */
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memset(blk_cfg, 0, sizeof(struct dma_block_config));
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blk_cfg->source_address = (uint32_t)&data->last_word;
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blk_cfg->dest_address = (uint32_t)&base->FIFOWR;
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blk_cfg->block_size = sizeof(uint32_t);
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blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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} else {
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blk_cfg->source_address = (uint32_t)buf;
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blk_cfg->dest_address = (uint32_t)&base->FIFOWR;
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blk_cfg->block_size = len;
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}
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}
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/* Enables the DMA request from SPI txFIFO */
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base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK;
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/* direction is given by the DT */
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stream->dma_cfg.head_block = &stream->dma_blk_cfg[0];
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/* give the client dev as arg, as the callback comes from the dma */
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stream->dma_cfg.user_data = data;
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/* pass our client origin to the dma: data->dma_tx.dma_channel */
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ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.channel,
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&stream->dma_cfg);
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/* the channel is the actual stream from 0 */
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if (ret != 0) {
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return ret;
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}
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uint32_t tmpData = 0U;
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spi_mcux_prepare_txdummy(&tmpData, last_packet, spi_cfg);
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/* Setup the control info.
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* Halfword writes to just the control bits (offset 0xE22) doesn't push
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* anything into the FIFO. And the data access type of control bits must
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* be uint16_t, byte writes or halfword writes to FIFOWR will push the
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* data and the current control bits into the FIFO.
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*/
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if ((last_packet) &&
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((word_size > 8) ? (len == 2U) : (len == 1U))) {
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*((uint16_t *)((uint32_t)&base->FIFOWR) + 1) = (uint16_t)(tmpData >> 16U);
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} else {
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/* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last */
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tmpData &= (~(uint32_t)SPI_FIFOWR_EOT_MASK);
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*((uint16_t *)((uint32_t)&base->FIFOWR) + 1) = (uint16_t)(tmpData >> 16U);
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}
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/* gives the request ID */
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return dma_start(data->dma_tx.dma_dev, data->dma_tx.channel);
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}
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static int spi_mcux_dma_rx_load(const struct device *dev, uint8_t *buf,
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size_t len)
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{
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const struct spi_mcux_config *cfg = dev->config;
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struct spi_mcux_data *data = dev->data;
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struct dma_block_config *blk_cfg;
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int ret;
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SPI_Type *base = cfg->base;
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/* retrieve active RX DMA channel (used in callback) */
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struct stream *stream = &data->dma_rx;
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blk_cfg = &stream->dma_blk_cfg[0];
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/* prepare the block for this RX DMA channel */
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memset(blk_cfg, 0, sizeof(struct dma_block_config));
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blk_cfg->block_size = len;
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/* rx direction has periph as source and mem as dest. */
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if (buf == NULL) {
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/* if rx buff is null, then write data to dummy address. */
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blk_cfg->dest_address = (uint32_t)&dummy_rx_buffer;
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} else {
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blk_cfg->dest_address = (uint32_t)buf;
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}
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blk_cfg->source_address = (uint32_t)&base->FIFORD;
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/* direction is given by the DT */
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stream->dma_cfg.head_block = blk_cfg;
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stream->dma_cfg.user_data = data;
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/* Enables the DMA request from SPI rxFIFO */
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base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK;
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/* pass our client origin to the dma: data->dma_rx.channel */
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ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.channel,
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&stream->dma_cfg);
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/* the channel is the actual stream from 0 */
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if (ret != 0) {
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return ret;
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}
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/* gives the request ID */
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return dma_start(data->dma_rx.dma_dev, data->dma_rx.channel);
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}
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static int spi_mcux_dma_move_buffers(const struct device *dev, size_t len,
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const struct spi_config *spi_cfg, bool last_packet)
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{
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struct spi_mcux_data *data = dev->data;
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int ret;
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ret = spi_mcux_dma_rx_load(dev, data->ctx.rx_buf, len);
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if (ret != 0) {
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return ret;
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}
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ret = spi_mcux_dma_tx_load(dev, data->ctx.tx_buf, spi_cfg,
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len, last_packet);
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return ret;
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}
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static int wait_dma_rx_tx_done(const struct device *dev)
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{
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struct spi_mcux_data *data = dev->data;
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int ret = -1;
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while (1) {
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ret = spi_context_wait_for_completion(&data->ctx);
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if (data->status_flags & SPI_MCUX_FLEXCOMM_DMA_ERROR_FLAG) {
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return -EIO;
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}
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if ((data->status_flags & SPI_MCUX_FLEXCOMM_DMA_DONE_FLAG) ==
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SPI_MCUX_FLEXCOMM_DMA_DONE_FLAG) {
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return 0;
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}
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}
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}
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static int transceive_dma(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous,
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struct k_poll_signal *signal)
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{
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const struct spi_mcux_config *config = dev->config;
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struct spi_mcux_data *data = dev->data;
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SPI_Type *base = config->base;
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int ret;
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uint32_t word_size;
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spi_context_lock(&data->ctx, asynchronous, signal);
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ret = spi_mcux_configure(dev, spi_cfg);
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if (ret) {
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goto out;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(&data->ctx, true);
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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data->dma_rx.dma_cfg.dest_data_size = (word_size > 8) ?
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(sizeof(uint16_t)) : (sizeof(uint8_t));
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data->dma_tx.dma_cfg.dest_data_size = data->dma_rx.dma_cfg.dest_data_size;
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while (data->ctx.rx_len > 0 || data->ctx.tx_len > 0) {
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size_t dma_len;
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bool last = false;
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if (data->ctx.rx_len == 0) {
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dma_len = data->ctx.tx_len;
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last = true;
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} else if (data->ctx.tx_len == 0) {
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dma_len = data->ctx.rx_len;
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last = true;
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} else if (data->ctx.tx_len == data->ctx.rx_len) {
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dma_len = data->ctx.rx_len;
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last = true;
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} else {
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dma_len = MIN(data->ctx.tx_len, data->ctx.rx_len);
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last = false;
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}
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data->status_flags = 0;
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ret = spi_mcux_dma_move_buffers(dev, dma_len, spi_cfg, last);
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if (ret != 0) {
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break;
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}
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ret = wait_dma_rx_tx_done(dev);
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if (ret != 0) {
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break;
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}
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/* wait until TX FIFO is really empty */
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while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) {
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}
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spi_context_update_tx(&data->ctx, 1, dma_len);
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spi_context_update_rx(&data->ctx, 1, dma_len);
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}
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base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK;
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base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK;
|
||||
|
||||
spi_context_cs_control(&data->ctx, false);
|
||||
|
||||
out:
|
||||
spi_context_release(&data->ctx, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static int transceive(const struct device *dev,
|
||||
const struct spi_config *spi_cfg,
|
||||
const struct spi_buf_set *tx_bufs,
|
||||
|
|
@ -257,6 +647,14 @@ static int spi_mcux_transceive(const struct device *dev,
|
|||
const struct spi_buf_set *tx_bufs,
|
||||
const struct spi_buf_set *rx_bufs)
|
||||
{
|
||||
#ifdef CONFIG_SPI_MCUX_FLEXCOMM_DMA
|
||||
struct spi_mcux_data *data = dev->data;
|
||||
|
||||
if ((data->dma_tx.dma_name != NULL)
|
||||
&& (data->dma_rx.dma_name != NULL)) {
|
||||
return transceive_dma(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL);
|
||||
}
|
||||
#endif
|
||||
return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL);
|
||||
}
|
||||
|
||||
|
|
@ -295,6 +693,25 @@ static int spi_mcux_init(const struct device *dev)
|
|||
|
||||
data->dev = dev;
|
||||
|
||||
#ifdef CONFIG_SPI_MCUX_FLEXCOMM_DMA
|
||||
if (data->dma_tx.dma_name != NULL) {
|
||||
/* Get the binding to the DMA device */
|
||||
data->dma_tx.dma_dev = device_get_binding(data->dma_tx.dma_name);
|
||||
if (!data->dma_tx.dma_dev) {
|
||||
LOG_ERR("%s device not found", data->dma_tx.dma_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
if (data->dma_rx.dma_name != NULL) {
|
||||
data->dma_rx.dma_dev = device_get_binding(data->dma_rx.dma_name);
|
||||
if (!data->dma_rx.dma_dev) {
|
||||
LOG_ERR("%s device not found", data->dma_rx.dma_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SPI_MCUX_FLEXCOMM_DMA */
|
||||
|
||||
spi_context_unlock_unconditionally(&data->ctx);
|
||||
|
||||
return 0;
|
||||
|
|
@ -308,19 +725,63 @@ static const struct spi_driver_api spi_mcux_driver_api = {
|
|||
.release = spi_mcux_release,
|
||||
};
|
||||
|
||||
#define SPI_MCUX_FLEXCOMM_IRQ_HANDLER_DECL(id) \
|
||||
static void spi_mcux_config_func_##id(const struct device *dev)
|
||||
#define SPI_MCUX_FLEXCOMM_IRQ_HANDLER_FUNC(id) \
|
||||
.irq_config_func = spi_mcux_config_func_##id,
|
||||
#define SPI_MCUX_FLEXCOMM_IRQ_HANDLER(id) \
|
||||
static void spi_mcux_config_func_##id(const struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_IRQN(id), \
|
||||
DT_INST_IRQ(id, priority), \
|
||||
spi_mcux_isr, DEVICE_GET(spi_mcux_##id), \
|
||||
0); \
|
||||
irq_enable(DT_INST_IRQN(id)); \
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SPI_MCUX_FLEXCOMM_DMA
|
||||
#define SPI_DMA_CHANNELS(id)
|
||||
#else
|
||||
#define SPI_DMA_CHANNELS(id) \
|
||||
.dma_tx = { \
|
||||
.dma_name = DT_INST_DMAS_LABEL_BY_NAME(id, tx), \
|
||||
.channel = \
|
||||
DT_INST_DMAS_CELL_BY_NAME(id, tx, channel), \
|
||||
.dma_cfg = { \
|
||||
.channel_direction = MEMORY_TO_PERIPHERAL, \
|
||||
.dma_callback = spi_mcux_dma_callback, \
|
||||
.source_data_size = 1, \
|
||||
.block_count = 2, \
|
||||
} \
|
||||
}, \
|
||||
.dma_rx = { \
|
||||
.dma_name = DT_INST_DMAS_LABEL_BY_NAME(id, rx), \
|
||||
.channel = \
|
||||
DT_INST_DMAS_CELL_BY_NAME(id, rx, channel), \
|
||||
.dma_cfg = { \
|
||||
.channel_direction = PERIPHERAL_TO_MEMORY, \
|
||||
.dma_callback = spi_mcux_dma_callback, \
|
||||
.source_data_size = 1, \
|
||||
.block_count = 1, \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#define SPI_MCUX_FLEXCOMM_DEVICE(id) \
|
||||
static void spi_mcux_config_func_##id(const struct device *dev); \
|
||||
SPI_MCUX_FLEXCOMM_IRQ_HANDLER_DECL(id); \
|
||||
static const struct spi_mcux_config spi_mcux_config_##id = { \
|
||||
.base = \
|
||||
(SPI_Type *)DT_INST_REG_ADDR(id), \
|
||||
.clock_name = DT_INST_CLOCKS_LABEL(id), \
|
||||
.clock_subsys = \
|
||||
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(id, name),\
|
||||
.irq_config_func = spi_mcux_config_func_##id, \
|
||||
SPI_MCUX_FLEXCOMM_IRQ_HANDLER_FUNC(id) \
|
||||
}; \
|
||||
static struct spi_mcux_data spi_mcux_data_##id = { \
|
||||
SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##id, ctx), \
|
||||
SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##id, ctx), \
|
||||
SPI_DMA_CHANNELS(id) \
|
||||
}; \
|
||||
DEVICE_AND_API_INIT(spi_mcux_##id, \
|
||||
DT_INST_LABEL(id), \
|
||||
|
|
@ -330,13 +791,7 @@ static const struct spi_driver_api spi_mcux_driver_api = {
|
|||
POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
||||
&spi_mcux_driver_api); \
|
||||
static void spi_mcux_config_func_##id(const struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_IRQN(id), \
|
||||
DT_INST_IRQ(id, priority), \
|
||||
spi_mcux_isr, DEVICE_GET(spi_mcux_##id), \
|
||||
0); \
|
||||
irq_enable(DT_INST_IRQN(id)); \
|
||||
}
|
||||
\
|
||||
SPI_MCUX_FLEXCOMM_IRQ_HANDLER(id)
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_FLEXCOMM_DEVICE)
|
||||
|
|
|
|||
|
|
@ -5,3 +5,5 @@
|
|||
#
|
||||
|
||||
CONFIG_SPI_LOOPBACK_DRV_NAME="FLEXCOMM_5"
|
||||
CONFIG_SPI_MCUX_FLEXCOMM_DMA=y
|
||||
CONFIG_SPI_ASYNC=n
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue