arm: Freescale K64 GPIO driver
Basic driver support for the Freescale K64 GPIO module. Note that only pin direction, read and write are supported. Change-Id: I6587bb260197a00497be9ac991002e3dde54718d Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
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Jeff Blais
Gerrit Code Review
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5 changed files with 432 additions and 1 deletions
233
drivers/gpio/gpio_k64.c
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233
drivers/gpio/gpio_k64.c
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/*
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* Copyright (c) 2016, Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Driver for the Freescale K64 GPIO module.
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*/
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#include <nanokernel.h>
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#include <device.h>
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#include <init.h>
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#include <gpio.h>
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#include "gpio_k64.h"
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static int gpio_k64_config(struct device *dev, int access_op,
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uint32_t pin, int flags)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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uint32_t value = 0;
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/*
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* Setup direction register:
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* 0 - pin is input, 1 - pin is output
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*/
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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sys_clear_bit((cfg->base_addr + GPIO_K64_DIR_OFFSET), pin);
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} else {
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sys_set_bit((cfg->base_addr + GPIO_K64_DIR_OFFSET), pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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value = 0x0;
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} else {
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value = 0xFFFFFFFF;
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}
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sys_write32(value, (cfg->base_addr + GPIO_K64_DIR_OFFSET));
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}
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return DEV_OK;
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}
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static int gpio_k64_write(struct device *dev, int access_op,
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uint32_t pin, uint32_t value)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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sys_set_bit((cfg->base_addr + GPIO_K64_DATA_OUT_OFFSET), pin);
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} else {
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sys_clear_bit((cfg->base_addr + GPIO_K64_DATA_OUT_OFFSET), pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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sys_write32(value, (cfg->base_addr + GPIO_K64_DATA_OUT_OFFSET));
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}
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return DEV_OK;
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}
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static int gpio_k64_read(struct device *dev, int access_op,
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uint32_t pin, uint32_t *value)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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*value = sys_read32((cfg->base_addr + GPIO_K64_DATA_IN_OFFSET));
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (*value & (1 << pin)) >> pin;
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}
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/* nothing more to do for GPIO_ACCESS_BY_PORT */
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return DEV_OK;
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}
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static int gpio_k64_set_callback(struct device *dev, gpio_callback_t callback)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(callback);
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return DEV_INVALID_OP;
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}
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static int gpio_k64_enable_callback(struct device *dev, int access_op,
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uint32_t pin)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pin);
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return DEV_INVALID_OP;
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}
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static int gpio_k64_disable_callback(struct device *dev, int access_op,
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uint32_t pin)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(access_op);
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ARG_UNUSED(pin);
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return DEV_INVALID_OP;
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}
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static int gpio_k64_suspend_port(struct device *dev)
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{
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ARG_UNUSED(dev);
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return DEV_INVALID_OP;
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}
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static int gpio_k64_resume_port(struct device *dev)
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{
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ARG_UNUSED(dev);
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return DEV_INVALID_OP;
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}
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static struct gpio_driver_api gpio_k64_drv_api_funcs = {
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.config = gpio_k64_config,
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.write = gpio_k64_write,
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.read = gpio_k64_read,
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.set_callback = gpio_k64_set_callback,
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.enable_callback = gpio_k64_enable_callback,
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.disable_callback = gpio_k64_disable_callback,
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.suspend = gpio_k64_suspend_port,
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.resume = gpio_k64_resume_port,
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};
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/**
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* @brief Initialization function of Freescale K64-based GPIO port
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*
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* @param dev Device structure pointer
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* @return DEV_OK if successful, failed otherwise.
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*/
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int gpio_k64_init(struct device *dev)
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{
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dev->driver_api = &gpio_k64_drv_api_funcs;
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return DEV_OK;
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}
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/* Initialization for Port A */
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#ifdef CONFIG_GPIO_K64_A
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static struct gpio_k64_config gpio_k64_A_cfg = {
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.base_addr = CONFIG_GPIO_K64_A_BASE_ADDR,
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};
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DEVICE_INIT(gpio_k64_A, CONFIG_GPIO_K64_A_DEV_NAME, gpio_k64_init,
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NULL, &gpio_k64_A_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_GPIO_K64_A */
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/* Initialization for Port B */
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#ifdef CONFIG_GPIO_K64_B
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static struct gpio_k64_config gpio_k64_B_cfg = {
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.base_addr = CONFIG_GPIO_K64_B_BASE_ADDR,
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};
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DEVICE_INIT(gpio_k64_B, CONFIG_GPIO_K64_B_DEV_NAME, gpio_k64_init,
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NULL, &gpio_k64_B_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_GPIO_K64_B */
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/* Initialization for Port C */
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#ifdef CONFIG_GPIO_K64_C
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static struct gpio_k64_config gpio_k64_C_cfg = {
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.base_addr = CONFIG_GPIO_K64_C_BASE_ADDR,
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};
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DEVICE_INIT(gpio_k64_C, CONFIG_GPIO_K64_C_DEV_NAME, gpio_k64_init,
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NULL, &gpio_k64_C_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_GPIO_K64_C */
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/* Initialization for Port D */
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#ifdef CONFIG_GPIO_K64_D
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static struct gpio_k64_config gpio_k64_D_cfg = {
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.base_addr = CONFIG_GPIO_K64_D_BASE_ADDR,
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};
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DEVICE_INIT(gpio_k64_D, CONFIG_GPIO_K64_D_DEV_NAME, gpio_k64_init,
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NULL, &gpio_k64_D_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_GPIO_K64_D */
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/* Initialization for Port E */
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#ifdef CONFIG_GPIO_K64_E
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static struct gpio_k64_config gpio_k64_E_cfg = {
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.base_addr = CONFIG_GPIO_K64_E_BASE_ADDR,
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};
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DEVICE_INIT(gpio_k64_E, CONFIG_GPIO_K64_E_DEV_NAME, gpio_k64_init,
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NULL, &gpio_k64_E_cfg,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_GPIO_K64_E */
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