drivers: ethernet: eth_mcux: add support for resetting phy
add support for resetting phy at boot via GPIO reset pin. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
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9824721680
commit
0f939d350d
15 changed files with 95 additions and 8 deletions
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@ -27,6 +27,9 @@ if NETWORKING
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config NET_L2_ETHERNET
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default y
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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endif # BOARD_MIMXRT1020_EVK
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@ -163,6 +163,8 @@ arduino_serial: &lpuart2 {
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status = "okay";
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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int-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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ptp {
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status = "okay";
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pinctrl-0 = <&pinmux_ptp>;
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@ -24,6 +24,9 @@ if NETWORKING
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config NET_L2_ETHERNET
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default y
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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endif # BOARD_MIMXRT1024_EVK
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@ -87,6 +87,8 @@
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status = "okay";
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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int-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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ptp {
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status = "okay";
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pinctrl-0 = <&pinmux_ptp>;
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@ -49,6 +49,9 @@ if NETWORKING
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config NET_L2_ETHERNET
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default y
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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if LVGL
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@ -243,6 +243,8 @@ arduino_serial: &lpuart3 {
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status = "okay";
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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ptp {
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pinctrl-0 = <&pinmux_ptp>;
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pinctrl-names = "default";
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@ -49,6 +49,9 @@ if NETWORKING
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config NET_L2_ETHERNET
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default y
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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if LVGL
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@ -196,6 +196,8 @@ arduino_serial: &lpuart3 {
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status = "okay";
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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ptp {
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pinctrl-0 = <&pinmux_ptp>;
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pinctrl-names = "default";
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@ -43,6 +43,9 @@ if NETWORKING
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config NET_L2_ETHERNET
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default y
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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if LVGL
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@ -252,6 +252,8 @@ arduino_serial: &lpuart3 {
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status = "okay";
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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ptp {
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pinctrl-0 = <&pinmux_ptp>;
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pinctrl-names = "default";
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@ -47,6 +47,9 @@ if NETWORKING
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config NET_L2_ETHERNET
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default y if CPU_CORTEX_M7 # No cache memory support is required for driver
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config ETH_MCUX_PHY_RESET
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default y
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endif # NETWORKING
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endif # BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4
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@ -128,6 +128,8 @@
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&enet {
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status = "okay";
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int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>;
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ptp {
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status = "okay";
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};
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@ -55,6 +55,12 @@ config ETH_MCUX_RX_BUFFERS
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help
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Set the number of RX buffers provided to the MCUX driver.
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config ETH_MCUX_PHY_RESET
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bool "Reset the PHY at boot"
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help
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Reset the ethernet PHY at boot. Requires dts properties int-gpios and
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reset-gpios to be present.
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config ETH_MCUX_TX_BUFFERS
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int "Number of MCUX TX buffers"
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default 1
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@ -49,6 +49,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include <drivers/clock_control.h>
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#endif
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#include <devicetree.h>
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#include <drivers/gpio.h>
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#if defined(CONFIG_PINCTRL)
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#include <drivers/pinctrl.h>
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#endif
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@ -215,6 +216,10 @@ struct eth_context {
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#if defined(CONFIG_PINCTRL)
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const struct pinctrl_dev_config *pincfg;
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#endif
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#if defined(CONFIG_ETH_MCUX_PHY_RESET)
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const struct gpio_dt_spec int_gpio;
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const struct gpio_dt_spec reset_gpio;
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#endif
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};
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/* Use ENET_FRAME_MAX_VLANFRAMELEN for VLAN frame size
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@ -1000,6 +1005,31 @@ static void eth_tx_thread(void *arg1, void *unused1, void *unused2)
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}
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}
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#if defined(CONFIG_ETH_MCUX_PHY_RESET)
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static int eth_phy_reset(const struct device *dev)
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{
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int err;
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struct eth_context *context = dev->data;
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/* pull up the ENET_INT before RESET. */
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err = gpio_pin_configure_dt(&context->int_gpio, GPIO_OUTPUT_ACTIVE);
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if (err) {
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return err;
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}
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return gpio_pin_configure_dt(&context->reset_gpio, GPIO_OUTPUT_INACTIVE);
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}
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static int eth_phy_init(const struct device *dev)
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{
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struct eth_context *context = dev->data;
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/* RESET PHY chip. */
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k_busy_wait(USEC_PER_MSEC * 500);
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return gpio_pin_set_dt(&context->reset_gpio, 1);
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}
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#endif
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static void eth_mcux_init(const struct device *dev)
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{
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struct eth_context *context = dev->data;
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@ -1100,7 +1130,12 @@ static int eth_init(const struct device *dev)
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struct eth_context *context = dev->data;
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#if defined(CONFIG_PINCTRL)
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int err;
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#endif
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err = pinctrl_apply_state(context->pincfg, PINCTRL_STATE_DEFAULT);
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if (err) {
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return err;
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}
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#endif /* CONFIG_PINCTRL */
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#if defined(CONFIG_NET_POWER_MANAGEMENT)
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const uint32_t inst = ENET_GetInstance(context->base);
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@ -1108,6 +1143,11 @@ static int eth_init(const struct device *dev)
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context->clock = enet_clocks[inst];
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#endif
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#if defined(CONFIG_ETH_MCUX_PHY_RESET)
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eth_phy_reset(dev);
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eth_phy_init(dev);
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#endif
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#if defined(CONFIG_PTP_CLOCK_MCUX)
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k_mutex_init(&context->ptp_mutex);
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#endif
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@ -1148,13 +1188,6 @@ static int eth_init(const struct device *dev)
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context->mac_addr[2], context->mac_addr[3],
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context->mac_addr[4], context->mac_addr[5]);
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#if defined(CONFIG_PINCTRL)
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err = pinctrl_apply_state(context->pincfg, PINCTRL_STATE_DEFAULT);
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if (err) {
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return err;
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}
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#endif /* CONFIG_PINCTRL */
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return 0;
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}
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@ -1529,6 +1562,14 @@ static void eth_mcux_err_isr(const struct device *dev)
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#define ETH_MCUX_PINCTRL_INIT(n)
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#endif
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#if defined(CONFIG_ETH_MCUX_PHY_RESET)
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#define ETH_MCUX_PHY_GPIOS(n) \
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.int_gpio = GPIO_DT_SPEC_INST_GET(n, int_gpios), \
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.reset_gpio = GPIO_DT_SPEC_INST_GET(n, reset_gpios),
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#else
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#define ETH_MCUX_PHY_GPIOS(n)
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#endif
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#define ETH_MCUX_INIT(n) \
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ETH_MCUX_GEN_MAC(n) \
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\
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.tx_frame_buf = tx_enet_frame_##n##_buf, \
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.rx_frame_buf = rx_enet_frame_##n##_buf, \
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ETH_MCUX_PINCTRL_INIT(n) \
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ETH_MCUX_PHY_GPIOS(n) \
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ETH_MCUX_MAC_ADDR(n) \
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ETH_MCUX_POWER(n) \
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}; \
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@ -16,3 +16,12 @@ properties:
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type: int
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description: Address of the phy controller
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required: true
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reset-gpios:
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type: phandle-array
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required: false
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description: GPIO to reset PHY. Reset signal is assumed active low.
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int-gpios:
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type: phandle-array
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required: false
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description:
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interrupt GPIO for PHY. Will be pulled high before reset is asserted.
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