soc: riscv: litex: Add helpers for accessing CSRs
Depending on LiteX configuration, CSRs (control&status registers) might be split into several consecutive registers. This introduces common helper functions for all LiteX drivers providing access to CSRs for a default LiteX configuration (data_width = 8bit, bus_width = 32bit). Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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@ -14,4 +14,46 @@
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#define RISCV_RAM_BASE DT_INST_0_MMIO_SRAM_BASE_ADDRESS
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#define RISCV_RAM_SIZE DT_INST_0_MMIO_SRAM_SIZE
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#ifndef _ASMLANGUAGE
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/* CSR access helpers */
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static inline unsigned char litex_read8(unsigned long addr)
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{
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return sys_read8(addr);
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}
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static inline unsigned short litex_read16(unsigned long addr)
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{
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return (sys_read8(addr) << 8)
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| sys_read8(addr + 0x4);
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}
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static inline unsigned int litex_read32(unsigned long addr)
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{
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return (sys_read8(addr) << 24)
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| (sys_read8(addr + 0x4) << 16)
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| (sys_read8(addr + 0x8) << 8)
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| sys_read8(addr + 0xc);
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}
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static inline void litex_write8(unsigned char value, unsigned long addr)
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{
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sys_write8(value, addr);
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}
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static inline void litex_write16(unsigned short value, unsigned long addr)
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{
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sys_write8(value >> 8, addr);
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sys_write8(value, addr + 0x4);
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}
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static inline void litex_write32(unsigned int value, unsigned long addr)
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{
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sys_write8(value >> 24, addr);
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sys_write8(value >> 16, addr + 0x4);
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sys_write8(value >> 8, addr + 0x8);
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sys_write8(value, addr + 0xC);
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}
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#endif /* _ASMLANGUAGE */
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#endif /* __RISCV32_LITEX_VEXRISCV_SOC_H_ */
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