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soc: riscv: litex: Add helpers for accessing CSRs

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Depending on LiteX configuration, CSRs
(control&status registers) might be split
into several consecutive registers.

This introduces common helper functions
for all LiteX drivers providing access
to CSRs for a default LiteX configuration
(data_width = 8bit, bus_width = 32bit).

Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This commit is contained in:
Mateusz Holenko 2019-10-10 13:56:13 +02:00 • committed by Maureen Helm
commit 0f4e21cae8
1 changed files with 42 additions and 0 deletions
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42
soc/riscv/litex-vexriscv/soc.h
View file

@ -14,4 +14,46 @@
#define RISCV_RAM_BASE DT_INST_0_MMIO_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE DT_INST_0_MMIO_SRAM_SIZE
#ifndef _ASMLANGUAGE
/* CSR access helpers */
static inline unsigned char litex_read8(unsigned long addr)
{
return sys_read8(addr);
}
static inline unsigned short litex_read16(unsigned long addr)
{
return (sys_read8(addr) << 8)
| sys_read8(addr + 0x4);
}
static inline unsigned int litex_read32(unsigned long addr)
{
return (sys_read8(addr) << 24)
| (sys_read8(addr + 0x4) << 16)
| (sys_read8(addr + 0x8) << 8)
| sys_read8(addr + 0xc);
}
static inline void litex_write8(unsigned char value, unsigned long addr)
{
sys_write8(value, addr);
}
static inline void litex_write16(unsigned short value, unsigned long addr)
{
sys_write8(value >> 8, addr);
sys_write8(value, addr + 0x4);
}
static inline void litex_write32(unsigned int value, unsigned long addr)
{
sys_write8(value >> 24, addr);
sys_write8(value >> 16, addr + 0x4);
sys_write8(value >> 8, addr + 0x8);
sys_write8(value, addr + 0xC);
}
#endif /* _ASMLANGUAGE */
#endif /* __RISCV32_LITEX_VEXRISCV_SOC_H_ */