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arch/xtensa: soc/xtensa/intel_adsp: Enable KERNEL_COHERENCE

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Implement the kernel "coherence" API on top of the linker
cached/uncached mapping work.

Add Xtensa handling for the stack coherence API.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2020-05-12 14:27:18 -07:00 • committed by Anas Nashif
commit 0e83961b21
7 changed files with 99 additions and 16 deletions
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5
soc/xtensa/intel_adsp/common/soc_mp.c
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@ -79,6 +79,11 @@ static void mp_entry2(void)
volatile int ie;
uint32_t idc_reg;
/* We don't know what the boot ROM might have touched and we
* don't care. Make sure it's not in our local cache.
*/
xthal_dcache_all_writeback_inv();
/* Copy over VECBASE from the main CPU for an initial value
* (will need to revisit this if we ever allow a user API to
* change interrupt vectors at runtime).