arch/xtensa: soc/xtensa/intel_adsp: Enable KERNEL_COHERENCE

Implement the kernel "coherence" API on top of the linker
cached/uncached mapping work.

Add Xtensa handling for the stack coherence API.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>

soc/xtensa/intel_adsp/Kconfig

@@ -5,6 +5,7 @@
 
 config SOC_FAMILY_INTEL_ADSP
 	bool
+	select ARCH_HAS_COHERENCE
 
 if SOC_FAMILY_INTEL_ADSP
 

soc/xtensa/intel_adsp/cavs_v15/linker.ld

@@ -202,16 +202,7 @@ _memmap_cacheattr_bp_allvalid = 0x22222222;
  * as cacheattr_set macro sets them both to the same set of
  * attributes.
  */
-#ifndef CONFIG_SMP
 _memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;
-#else
-/*
- * FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP
- * since there is no data cache manipulation for spinlock, kernel
- * object, scheduler, etc...
- */
-_memmap_cacheattr_intel_cavs15_adsp = 0xFF22FFF2;
-#endif
 
 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);
 SECTIONS
@@ -426,7 +417,7 @@ SECTIONS
     *(.noinit.*)
   } >ram :ram_phdr
 
-  .lit4 SEGSTART_CACHED : ALIGN(4)
+  .lit4 : ALIGN(4)
   {
     _lit4_start = ABSOLUTE(.);
     *(*.lit4)
@@ -466,11 +457,13 @@ SECTIONS
 #define ROMABLE_REGION ucram :ucram_phdr
 #include <linker/common-ram.ld>
 
-  /* ANDY TEST */
-  .ucram SEGSTART_UNCACHED :
+  /* This section is cached.  By default it contains only declared
+   * thread stacks, but applications can put symbols here too.
+   */
+  .cached SEGSTART_CACHED :
   {
-    *(.ucram)
-  } >ucram :ucram_phdr
+    *(.cached .cached.*)
+  } >ram :ram_phdr
 
   .bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096)
   {

soc/xtensa/intel_adsp/common/soc_mp.c

@@ -79,6 +79,11 @@ static void mp_entry2(void)
 	volatile int ie;
 	uint32_t idc_reg;
 
+	/* We don't know what the boot ROM might have touched and we
+	 * don't care.  Make sure it's not in our local cache.
+	 */
+	xthal_dcache_all_writeback_inv();
+
 	/* Copy over VECBASE from the main CPU for an initial value
 	 * (will need to revisit this if we ever allow a user API to
 	 * change interrupt vectors at runtime).